| /external/u-boot/drivers/ddr/marvell/axp/ |
| D | ddr3_dfs.c | 70 u32 reg; in wait_refresh_op_complete() local
74 reg = reg_read(REG_SDRAM_OPERATION_ADDR) & in wait_refresh_op_complete()
76 } while (reg); /* Wait for '0' */ in wait_refresh_op_complete()
116 u32 reg, freq_par, tmp; in ddr3_dfs_high_2_low() local
132 reg = reg_read(REG_DFS_ADDR); in ddr3_dfs_high_2_low()
134 reg |= (1 << REG_DFS_DLLNEXTSTATE_OFFS); in ddr3_dfs_high_2_low()
135 dfs_reg_write(REG_DFS_ADDR, reg); /* 0x1528 - DFS register */ in ddr3_dfs_high_2_low()
141 reg = reg_read(REG_METAL_MASK_ADDR); in ddr3_dfs_high_2_low()
143 reg &= ~(1 << REG_METAL_MASK_RETRY_OFFS); in ddr3_dfs_high_2_low()
145 dfs_reg_write(REG_METAL_MASK_ADDR, reg); in ddr3_dfs_high_2_low()
[all …]
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| D | ddr3_write_leveling.c | 66 u32 reg, phase, delay, cs, pup; in ddr3_write_leveling_hw() local
75 reg = reg_read(REG_DUNIT_CTRL_LOW_ADDR); in ddr3_write_leveling_hw()
76 if (reg & (1 << REG_DUNIT_CTRL_LOW_DPDE_OFFS)) { in ddr3_write_leveling_hw()
79 reg & ~(1 << REG_DUNIT_CTRL_LOW_DPDE_OFFS)); in ddr3_write_leveling_hw()
83 reg = 1 << REG_DRAM_TRAINING_WL_OFFS; in ddr3_write_leveling_hw()
85 reg |= (COUNT_HW_WL << REG_DRAM_TRAINING_RETEST_OFFS); in ddr3_write_leveling_hw()
86 reg |= (dram_info->cs_ena << (REG_DRAM_TRAINING_CS_OFFS)); in ddr3_write_leveling_hw()
87 reg_write(REG_DRAM_TRAINING_ADDR, reg); /* 0x15B0 - Training Register */ in ddr3_write_leveling_hw()
89 reg = reg_read(REG_DRAM_TRAINING_SHADOW_ADDR) | in ddr3_write_leveling_hw()
91 reg_write(REG_DRAM_TRAINING_SHADOW_ADDR, reg); in ddr3_write_leveling_hw()
[all …]
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| /external/u-boot/drivers/video/exynos/ |
| D | exynos_dp_lowlevel.c | 22 unsigned int reg; in exynos_dp_enable_video_input() local
24 reg = readl(&dp_regs->video_ctl1); in exynos_dp_enable_video_input()
25 reg &= ~VIDEO_EN_MASK; in exynos_dp_enable_video_input()
29 reg |= VIDEO_EN_MASK; in exynos_dp_enable_video_input()
31 writel(reg, &dp_regs->video_ctl1); in exynos_dp_enable_video_input()
39 unsigned int reg; in exynos_dp_enable_video_bist() local
41 reg = readl(&dp_regs->video_ctl4); in exynos_dp_enable_video_bist()
42 reg &= ~VIDEO_BIST_MASK; in exynos_dp_enable_video_bist()
46 reg |= VIDEO_BIST_MASK; in exynos_dp_enable_video_bist()
48 writel(reg, &dp_regs->video_ctl4); in exynos_dp_enable_video_bist()
[all …]
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| D | exynos_mipi_dsi_lowlevel.c | 20 unsigned int reg; in exynos_mipi_dsi_func_reset() local
25 reg = readl(&mipi_dsim->swrst); in exynos_mipi_dsi_func_reset()
27 reg |= DSIM_FUNCRST; in exynos_mipi_dsi_func_reset()
29 writel(reg, &mipi_dsim->swrst); in exynos_mipi_dsi_func_reset()
34 unsigned int reg = 0; in exynos_mipi_dsi_sw_reset() local
39 reg = readl(&mipi_dsim->swrst); in exynos_mipi_dsi_sw_reset()
41 reg |= DSIM_SWRST; in exynos_mipi_dsi_sw_reset()
42 reg |= DSIM_FUNCRST; in exynos_mipi_dsi_sw_reset()
44 writel(reg, &mipi_dsim->swrst); in exynos_mipi_dsi_sw_reset()
51 unsigned int reg = readl(&mipi_dsim->intsrc); in exynos_mipi_dsi_sw_release() local
[all …]
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| /external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/MSP430/ |
| D | BranchSelector.ll | 5 @reg = common global i16 0, align 2
12 store volatile i16 11, i16* @reg, align 2
13 store volatile i16 13, i16* @reg, align 2
14 store volatile i16 17, i16* @reg, align 2
15 store volatile i16 11, i16* @reg, align 2
16 store volatile i16 13, i16* @reg, align 2
17 store volatile i16 17, i16* @reg, align 2
18 store volatile i16 11, i16* @reg, align 2
19 store volatile i16 13, i16* @reg, align 2
20 store volatile i16 17, i16* @reg, align 2
[all …]
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| /external/linux-kselftest/tools/testing/selftests/powerpc/include/ |
| D | vmx_asm.h | 13 #define PUSH_VMX(pos,reg) \ argument
14 li reg,pos; \
15 stvx v20,reg,%r1; \
16 addi reg,reg,16; \
17 stvx v21,reg,%r1; \
18 addi reg,reg,16; \
19 stvx v22,reg,%r1; \
20 addi reg,reg,16; \
21 stvx v23,reg,%r1; \
22 addi reg,reg,16; \
[all …]
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| /external/u-boot/arch/arm/dts/ |
| D | armada-38x-controlcenterdc.dts | 59 reg = <0x00000000 0x10000000>; /* 256 MB */
79 reg = <0>;
96 reg = <0>; /* Chip select 0 */
103 reg = <1>; /* Chip select 1 */
115 reg = <0x21>;
122 reg = <0x22>;
128 reg = <0x23>;
134 reg = <0x24>;
140 reg = <0x25>;
146 reg = <0x26>;
[all …]
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| /external/gemmlowp/internal/ |
| D | output_sse.h | 38 __m128i res_16 = _mm_packs_epi32(input.reg[0], input.reg[0]);
40 output.reg[0] = _mm_cvtsi128_si32(res_8);
57 __m128i res_16 = _mm_packs_epi32(input.reg[0], input.reg[1]);
59 output.reg[0] = _mm_extract_epi32(res_8, 0);
60 output.reg[1] = _mm_extract_epi32(res_8, 1);
77 __m128i res_16_0 = _mm_packs_epi32(input.reg[0], input.reg[1]);
78 __m128i res_16_1 = _mm_packs_epi32(input.reg[2], input.reg[3]);
79 output.reg[0] = _mm_packus_epi16(res_16_0, res_16_1);
96 __m128i res_16_0 = _mm_packs_epi32(input.reg[0], input.reg[1]);
97 __m128i res_16_1 = _mm_packs_epi32(input.reg[2], input.reg[3]);
[all …]
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| D | simd_wrappers_common_neon_sse.h | 32 result.buf.reg[i] = LoadInt32x4(src.data(row, col + i));
46 result.buf.reg[2 * i + 0] = LoadInt32x4(src.data(row + 0, col + i));
47 result.buf.reg[2 * i + 1] = LoadInt32x4(src.data(row + 4, col + i));
64 result.buf.reg[0] = LoadInt32x4(buf);
80 result.buf.reg[0] = LoadInt32x4(buf);
81 result.buf.reg[1] = LoadInt32x4(buf + 4);
92 result.buf.reg[0] = LoadInt32x4(src.data(pos));
103 result.buf.reg[0] = LoadInt32x4(src(0));
120 result.buf.reg[0] = LoadInt32x4(src.data(pos));
137 result.buf.reg[0] = LoadInt32x4(src.data(pos));
[all …]
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| D | output_neon.h | 38 int16x4_t res_16 = vqmovn_s32(input.reg[0]);
40 output.reg[0] = vget_lane_u32(vreinterpret_u32_u8(res_8), 0);
58 vcombine_s16(vqmovn_s32(input.reg[0]), vqmovn_s32(input.reg[1]));
59 output.reg[0] = vqmovun_s16(res_16);
77 vcombine_s16(vqmovn_s32(input.reg[0]), vqmovn_s32(input.reg[1]));
79 vcombine_s16(vqmovn_s32(input.reg[2]), vqmovn_s32(input.reg[3]));
80 output.reg[0] = vqmovun_s16(res_16_0);
81 output.reg[1] = vqmovun_s16(res_16_1);
100 res_16[i] = vcombine_s16(vqmovn_s32(input.reg[2 * i]),
101 vqmovn_s32(input.reg[2 * i + 1]));
[all …]
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| D | output_msa.h | 40 v4i32 tmp = __builtin_msa_sat_s_w(input.reg[0], 8);
54 output.reg[0] = __builtin_msa_copy_s_w(tmp, 0);
73 v4i32 tmp_lo = __builtin_msa_sat_s_w(input.reg[0], 8);
74 v4i32 tmp_hi = __builtin_msa_sat_s_w(input.reg[1], 8);
89 output.reg[0] = __builtin_msa_copy_s_w(tmp_lo, 0);
90 output.reg[1] = __builtin_msa_copy_s_w(tmp_lo, 1);
128 GEMMLOWP_MIPS_SAT_U8_16(output.reg[0], input.reg[0], input.reg[1],
129 input.reg[2], input.reg[3]);
146 GEMMLOWP_MIPS_SAT_U8_16(output.reg[0], input.reg[0], input.reg[1],
147 input.reg[2], input.reg[3]);
[all …]
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| /external/u-boot/arch/arm/mach-imx/mx6/ |
| D | clock.c | 29 u32 reg; in enable_ocotp_clk() local
31 reg = __raw_readl(&imx_ccm->CCGR2); in enable_ocotp_clk()
33 reg |= MXC_CCM_CCGR2_OCOTP_CTRL_MASK; in enable_ocotp_clk()
35 reg &= ~MXC_CCM_CCGR2_OCOTP_CTRL_MASK; in enable_ocotp_clk()
36 __raw_writel(reg, &imx_ccm->CCGR2); in enable_ocotp_clk()
83 u32 reg; in enable_usboh3_clk() local
85 reg = __raw_readl(&imx_ccm->CCGR6); in enable_usboh3_clk()
87 reg |= MXC_CCM_CCGR6_USBOH3_MASK; in enable_usboh3_clk()
89 reg &= ~(MXC_CCM_CCGR6_USBOH3_MASK); in enable_usboh3_clk()
90 __raw_writel(reg, &imx_ccm->CCGR6); in enable_usboh3_clk()
[all …]
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| /external/u-boot/arch/arm/cpu/armv8/fsl-layerscape/ |
| D | fsl_lsch2_serdes.c | 150 u32 cfg_tmp, reg = 0; in setup_serdes_volt() local
180 reg = in_be32(&serdes1_base->lane[i].gcr0); in setup_serdes_volt()
181 reg &= 0xFF9FFFFF; in setup_serdes_volt()
182 out_be32(&serdes1_base->lane[i].gcr0, reg); in setup_serdes_volt()
190 reg = in_be32(&serdes2_base->lane[i].gcr0); in setup_serdes_volt()
191 reg &= 0xFF9FFFFF; in setup_serdes_volt()
192 out_be32(&serdes2_base->lane[i].gcr0, reg); in setup_serdes_volt()
200 reg = in_be32(&serdes1_base->bank[i].rstctl); in setup_serdes_volt()
201 reg &= 0xFFFFFFBF; in setup_serdes_volt()
202 reg |= 0x10000000; in setup_serdes_volt()
[all …]
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| /external/u-boot/arch/arm/mach-tegra/tegra20/ |
| D | warmboot_avp.c | 34 u32 reg; in wb_start() local
42 : "=r"(reg) /* output */ in wb_start()
46 if (reg != NV_WB_RUN_ADDRESS) in wb_start()
55 reg = readl(&clkrst->crc_rst_dev[TEGRA_DEV_U]); in wb_start()
56 reg |= SWR_CSITE_RST; in wb_start()
57 writel(reg, &clkrst->crc_rst_dev[TEGRA_DEV_U]); in wb_start()
68 reg = PWRGATE_TOGGLE_PARTID_CPU | PWRGATE_TOGGLE_START; in wb_start()
69 writel(reg, &pmc->pmc_pwrgate_toggle); in wb_start()
75 reg = readl(&pmc->pmc_remove_clamping); in wb_start()
76 reg |= CPU_CLMP; in wb_start()
[all …]
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| /external/mesa3d/src/intel/compiler/ |
| D | brw_reg.h | 356 struct brw_reg reg; in brw_reg() local
366 reg.type = type; in brw_reg()
367 reg.file = file; in brw_reg()
368 reg.negate = negate; in brw_reg()
369 reg.abs = abs; in brw_reg()
370 reg.address_mode = BRW_ADDRESS_DIRECT; in brw_reg()
371 reg.pad0 = 0; in brw_reg()
372 reg.subnr = subnr * type_sz(type); in brw_reg()
373 reg.nr = nr; in brw_reg()
381 reg.swizzle = swizzle; in brw_reg()
[all …]
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| D | brw_clip_line.c | 45 c->reg.R0 = retype(brw_vec8_grf(i, 0), BRW_REGISTER_TYPE_UD); i++; in brw_clip_line_alloc_regs()
48 c->reg.fixed_planes = brw_vec4_grf(i, 0); in brw_clip_line_alloc_regs()
60 c->reg.vertex[j] = brw_vec4_grf(i, 0); in brw_clip_line_alloc_regs()
64 c->reg.t = brw_vec1_grf(i, 0); in brw_clip_line_alloc_regs()
65 c->reg.t0 = brw_vec1_grf(i, 1); in brw_clip_line_alloc_regs()
66 c->reg.t1 = brw_vec1_grf(i, 2); in brw_clip_line_alloc_regs()
67 c->reg.planemask = retype(brw_vec1_grf(i, 3), BRW_REGISTER_TYPE_UD); in brw_clip_line_alloc_regs()
68 c->reg.plane_equation = brw_vec4_grf(i, 4); in brw_clip_line_alloc_regs()
71 c->reg.dp0 = brw_vec1_grf(i, 0); /* fixme - dp4 will clobber r.1,2,3 */ in brw_clip_line_alloc_regs()
72 c->reg.dp1 = brw_vec1_grf(i, 4); in brw_clip_line_alloc_regs()
[all …]
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| D | brw_ir_fs.h | 39 fs_reg(struct ::brw_reg reg);
57 negate(fs_reg reg) in negate() argument
59 assert(reg.file != IMM); in negate()
60 reg.negate = !reg.negate; in negate()
61 return reg; in negate()
65 retype(fs_reg reg, enum brw_reg_type type) in retype() argument
67 reg.type = type; in retype()
68 return reg; in retype()
72 byte_offset(fs_reg reg, unsigned delta) in byte_offset() argument
74 switch (reg.file) { in byte_offset()
[all …]
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| /external/mesa3d/src/mesa/state_tracker/ |
| D | st_glsl_to_tgsi_private.cpp | 53 st_src_reg *reg = ralloc(input, st_src_reg); in dup_reladdr() local
54 if (!reg) { in dup_reladdr()
59 *reg = *input; in dup_reladdr()
60 return reg; in dup_reladdr()
135 st_src_reg::st_src_reg(const st_src_reg ®) in st_src_reg() argument
137 *this = reg; in st_src_reg()
140 void st_src_reg::operator=(const st_src_reg ®) in operator =() argument
142 this->type = reg.type; in operator =()
143 this->file = reg.file; in operator =()
144 this->index = reg.index; in operator =()
[all …]
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| /external/virglrenderer/src/gallium/auxiliary/tgsi/ |
| D | tgsi_sanity.c | 66 scan_register_key(const scan_register *reg) in scan_register_key() argument
68 unsigned key = reg->file; in scan_register_key()
69 key |= (reg->indices[0] << 4); in scan_register_key()
70 key |= (reg->indices[1] << 18); in scan_register_key()
76 fill_scan_register1d(scan_register *reg, in fill_scan_register1d() argument
79 reg->file = file; in fill_scan_register1d()
80 reg->dimensions = 1; in fill_scan_register1d()
81 reg->indices[0] = index; in fill_scan_register1d()
82 reg->indices[1] = 0; in fill_scan_register1d()
86 fill_scan_register2d(scan_register *reg, in fill_scan_register2d() argument
[all …]
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| /external/mesa3d/src/gallium/auxiliary/tgsi/ |
| D | tgsi_sanity.c | 67 scan_register_key(const scan_register *reg) in scan_register_key() argument
69 unsigned key = reg->file; in scan_register_key()
70 key |= (reg->indices[0] << 4); in scan_register_key()
71 key |= (reg->indices[1] << 18); in scan_register_key()
77 fill_scan_register1d(scan_register *reg, in fill_scan_register1d() argument
80 reg->file = file; in fill_scan_register1d()
81 reg->dimensions = 1; in fill_scan_register1d()
82 reg->indices[0] = index; in fill_scan_register1d()
83 reg->indices[1] = 0; in fill_scan_register1d()
87 fill_scan_register2d(scan_register *reg, in fill_scan_register2d() argument
[all …]
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| /external/u-boot/drivers/spi/ |
| D | cadence_qspi_apb.c | 189 unsigned int reg; in cadence_qspi_apb_controller_enable() local
190 reg = readl(reg_base + CQSPI_REG_CONFIG); in cadence_qspi_apb_controller_enable()
191 reg |= CQSPI_REG_CONFIG_ENABLE; in cadence_qspi_apb_controller_enable()
192 writel(reg, reg_base + CQSPI_REG_CONFIG); in cadence_qspi_apb_controller_enable()
197 unsigned int reg; in cadence_qspi_apb_controller_disable() local
198 reg = readl(reg_base + CQSPI_REG_CONFIG); in cadence_qspi_apb_controller_disable()
199 reg &= ~CQSPI_REG_CONFIG_ENABLE; in cadence_qspi_apb_controller_disable()
200 writel(reg, reg_base + CQSPI_REG_CONFIG); in cadence_qspi_apb_controller_disable()
233 unsigned int reg; in cadence_qspi_apb_readdata_capture() local
236 reg = readl(reg_base + CQSPI_REG_RD_DATA_CAPTURE); in cadence_qspi_apb_readdata_capture()
[all …]
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| /external/u-boot/drivers/watchdog/ |
| D | orion_wdt.c | 25 void __iomem *reg; member
47 writel(priv->timeout, priv->reg + priv->wdt_counter_offset); in orion_wdt_reset()
55 u32 reg; in orion_wdt_start() local
60 reg = readl(priv->reg + TIMER_CTRL); in orion_wdt_start()
61 reg |= WDT_AXP_FIXED_ENABLE_BIT; in orion_wdt_start()
62 writel(reg, priv->reg + TIMER_CTRL); in orion_wdt_start()
65 writel(priv->timeout, priv->reg + priv->wdt_counter_offset); in orion_wdt_start()
68 reg = readl(priv->reg + TIMER_A370_STATUS); in orion_wdt_start()
69 reg &= ~WDT_A370_EXPIRED; in orion_wdt_start()
70 writel(reg, priv->reg + TIMER_A370_STATUS); in orion_wdt_start()
[all …]
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| /external/u-boot/drivers/pci/ |
| D | pci-aardvark.c | 121 #define PCIE_CONF_REG(reg) ((reg) & 0xffc) argument
150 static inline void advk_writel(struct pcie_advk *pcie, uint val, uint reg) in advk_writel() argument
152 writel(val, pcie->base + reg); in advk_writel()
155 static inline uint advk_readl(struct pcie_advk *pcie, uint reg) in advk_readl() argument
157 return readl(pcie->base + reg); in advk_readl()
224 uint reg; in pcie_advk_check_pio_status() local
228 reg = advk_readl(pcie, PIO_STAT); in pcie_advk_check_pio_status()
229 status = (reg & PIO_COMPLETION_STATUS_MASK) >> in pcie_advk_check_pio_status()
234 if (reg & PIO_ERR_STATUS) { in pcie_advk_check_pio_status()
273 if (reg & PIO_NON_POSTED_REQ) in pcie_advk_check_pio_status()
[all …]
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| /external/u-boot/drivers/video/ |
| D | ipu_disp.c | 183 u32 reg; in ipu_di_data_wave_config() local
184 reg = (access_size << DI_DW_GEN_ACCESS_SIZE_OFFSET) | in ipu_di_data_wave_config()
186 __raw_writel(reg, DI_DW_GEN(di, wave_gen)); in ipu_di_data_wave_config()
192 u32 reg; in ipu_di_data_pin_config() local
194 reg = __raw_readl(DI_DW_GEN(di, wave_gen)); in ipu_di_data_pin_config()
195 reg &= ~(0x3 << (di_pin * 2)); in ipu_di_data_pin_config()
196 reg |= set << (di_pin * 2); in ipu_di_data_pin_config()
197 __raw_writel(reg, DI_DW_GEN(di, wave_gen)); in ipu_di_data_pin_config()
211 u32 reg; in ipu_di_sync_config() local
220 reg = (run_count << 19) | (++run_src << 16) | in ipu_di_sync_config()
[all …]
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| /external/u-boot/arch/arm/mach-socfpga/ |
| D | clock_manager_gen5.c | 320 u32 reg, clock; in cm_get_main_vco_clk_hz() local
323 reg = readl(&clock_manager_base->main_pll.vco); in cm_get_main_vco_clk_hz()
325 clock /= ((reg & CLKMGR_MAINPLLGRP_VCO_DENOM_MASK) >> in cm_get_main_vco_clk_hz()
327 clock *= ((reg & CLKMGR_MAINPLLGRP_VCO_NUMER_MASK) >> in cm_get_main_vco_clk_hz()
335 u32 reg, clock = 0; in cm_get_per_vco_clk_hz() local
338 reg = readl(&clock_manager_base->per_pll.vco); in cm_get_per_vco_clk_hz()
339 reg = (reg & CLKMGR_PERPLLGRP_VCO_SSRC_MASK) >> in cm_get_per_vco_clk_hz()
341 if (reg == CLKMGR_VCO_SSRC_EOSC1) in cm_get_per_vco_clk_hz()
343 else if (reg == CLKMGR_VCO_SSRC_EOSC2) in cm_get_per_vco_clk_hz()
345 else if (reg == CLKMGR_VCO_SSRC_F2S) in cm_get_per_vco_clk_hz()
[all …]
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