| /external/libvpx/libvpx/vpx_dsp/mips/ |
| D | idct16x16_msa.c | 16 v8i16 reg3, reg13, reg11, reg5, reg7, reg9, reg1, reg15; in vpx_idct16_1d_rows_msa() local
21 LD_SH8(input, 16, reg8, reg9, reg10, reg11, reg12, reg13, reg14, reg15); in vpx_idct16_1d_rows_msa()
25 TRANSPOSE8x8_SH_SH(reg8, reg9, reg10, reg11, reg12, reg13, reg14, reg15, reg8, in vpx_idct16_1d_rows_msa()
26 reg9, reg10, reg11, reg12, reg13, reg14, reg15); in vpx_idct16_1d_rows_msa()
48 DOTP_CONST_PAIR(reg5, reg11, cospi_22_64, cospi_10_64, reg5, reg11); in vpx_idct16_1d_rows_msa()
50 BUTTERFLY_4(loc0, loc1, reg11, reg5, reg13, reg3, reg11, reg5); in vpx_idct16_1d_rows_msa()
66 DOTP_CONST_PAIR((-reg5), (-reg11), cospi_8_64, cospi_24_64, reg5, reg11); in vpx_idct16_1d_rows_msa()
73 loc0 = reg7 + reg11; in vpx_idct16_1d_rows_msa()
74 reg11 = reg7 - reg11; in vpx_idct16_1d_rows_msa()
79 DOTP_CONST_PAIR(reg5, reg11, cospi_16_64, cospi_16_64, reg5, reg11); in vpx_idct16_1d_rows_msa()
[all …]
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| /external/u-boot/board/freescale/c29xpcie/ |
| D | cpld.c | 28 u8 reg11; in cpld_set_altbank() local
30 reg11 = in_8(&cpld_data->flhcsr); in cpld_set_altbank()
34 out_8(&cpld_data->flhcsr, (reg11 & CPLD_BANKSEL_MASK) in cpld_set_altbank()
38 out_8(&cpld_data->flhcsr, (reg11 & CPLD_BANKSEL_MASK) in cpld_set_altbank()
42 out_8(&cpld_data->flhcsr, (reg11 & CPLD_BANKSEL_MASK) in cpld_set_altbank()
46 out_8(&cpld_data->flhcsr, (reg11 & CPLD_BANKSEL_MASK) in cpld_set_altbank()
|
| /external/u-boot/Documentation/devicetree/bindings/phy/ |
| D | phy-stm32-usbphyc.txt | 61 vdda1v1-supply = <®11>;
69 vdda1v1-supply = <®11>;
|
| /external/u-boot/arch/arm/dts/ |
| D | stm32mp157.dtsi | 139 reg11: reg11 { label
140 regulator-name = "reg11";
|
| /external/libvpx/libvpx/third_party/libyuv/source/ |
| D | scale_msa.cc | 767 v8i16 reg6, reg7, reg8, reg9, reg10, reg11; in ScaleRowDown34_0_Box_MSA() local
813 reg11 = (v8i16)__msa_dotp_u_h(vec11, const2); in ScaleRowDown34_0_Box_MSA()
825 reg11 = __msa_srar_h(reg11, shft2); in ScaleRowDown34_0_Box_MSA()
831 reg5 = reg5 * 3 + reg11; in ScaleRowDown34_0_Box_MSA()
861 v8i16 reg6, reg7, reg8, reg9, reg10, reg11; in ScaleRowDown34_1_Box_MSA() local
907 reg11 = (v8i16)__msa_dotp_u_h(vec11, const2); in ScaleRowDown34_1_Box_MSA()
919 reg11 = __msa_srar_h(reg11, shft2); in ScaleRowDown34_1_Box_MSA()
925 reg5 += reg11; in ScaleRowDown34_1_Box_MSA()
|
| /external/elfutils/tests/ |
| D | run-addrcfi.sh | 44 x87 reg11 (%st0): undefined
91 x87 reg11 (%st0): undefined
143 integer reg11 (%r11): undefined
209 integer reg11 (%r11): undefined
313 integer reg11 (r11): undefined
1335 integer reg11 (r11): undefined
2363 integer reg11 (r11): undefined
3389 integer reg11 (%r11): same_value
3466 integer reg11 (%r11): same_value
3544 integer reg11 (r11): same_value
[all …]
|
| /external/llvm/include/llvm/Support/ |
| D | Dwarf.def | 212 HANDLE_DW_OP(0x5b, reg11)
|
| /external/elfutils/libdw/ |
| D | known-dwarf.h | 501 DWARF_ONE_KNOWN_DW_OP (reg11, DW_OP_reg11) \
|
| /external/swiftshader/third_party/llvm-7.0/llvm/include/llvm/BinaryFormat/ |
| D | Dwarf.def | 535 HANDLE_DW_OP(0x5b, reg11, 2, DWARF)
|