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Searched refs:reg7 (Results 1 – 25 of 26) sorted by relevance

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/external/libvpx/libvpx/vpx_dsp/mips/
Didct32x32_msa.c44 v8i16 reg0, reg1, reg2, reg3, reg4, reg5, reg6, reg7; in idct32x8_row_even_process_store() local
48 LD_SH8(tmp_buf, 32, reg0, reg1, reg2, reg3, reg4, reg5, reg6, reg7); in idct32x8_row_even_process_store()
50 DOTP_CONST_PAIR(reg1, reg7, cospi_28_64, cospi_4_64, reg1, reg7); in idct32x8_row_even_process_store()
52 BUTTERFLY_4(reg1, reg7, reg3, reg5, vec1, vec3, vec2, vec0); in idct32x8_row_even_process_store()
65 LD_SH8((tmp_buf + 16), 32, reg0, reg1, reg2, reg3, reg4, reg5, reg6, reg7); in idct32x8_row_even_process_store()
66 DOTP_CONST_PAIR(reg0, reg7, cospi_30_64, cospi_2_64, reg0, reg7); in idct32x8_row_even_process_store()
77 reg5 = reg7 + reg3; in idct32x8_row_even_process_store()
78 reg7 = reg7 - reg3; in idct32x8_row_even_process_store()
87 DOTP_CONST_PAIR(reg7, reg0, cospi_24_64, cospi_8_64, reg0, reg7); in idct32x8_row_even_process_store()
92 vec1 = reg7 - reg1; in idct32x8_row_even_process_store()
[all …]
Didct16x16_msa.c16 v8i16 reg3, reg13, reg11, reg5, reg7, reg9, reg1, reg15; in vpx_idct16_1d_rows_msa() local
19 LD_SH8(input, 16, reg0, reg1, reg2, reg3, reg4, reg5, reg6, reg7); in vpx_idct16_1d_rows_msa()
23 TRANSPOSE8x8_SH_SH(reg0, reg1, reg2, reg3, reg4, reg5, reg6, reg7, reg0, reg1, in vpx_idct16_1d_rows_msa()
24 reg2, reg3, reg4, reg5, reg6, reg7); in vpx_idct16_1d_rows_msa()
41 DOTP_CONST_PAIR(reg9, reg7, cospi_14_64, cospi_18_64, loc2, loc3); in vpx_idct16_1d_rows_msa()
45 reg7 = reg15 - loc3; in vpx_idct16_1d_rows_msa()
65 DOTP_CONST_PAIR(reg7, reg9, cospi_24_64, cospi_8_64, reg7, reg9); in vpx_idct16_1d_rows_msa()
73 loc0 = reg7 + reg11; in vpx_idct16_1d_rows_msa()
74 reg11 = reg7 - reg11; in vpx_idct16_1d_rows_msa()
86 BUTTERFLY_4(reg12, reg14, reg13, reg3, reg8, reg6, reg7, reg5); in vpx_idct16_1d_rows_msa()
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/external/elfutils/tests/
Drun-dwarfcfi.sh45 reg7: same_value
62 reg7: location expression: call_frame_cfa stack_value
79 reg7: undefined
96 reg7: undefined
113 reg7: same_value
130 reg7: undefined
Drun-addrcfi.sh40 integer reg7 (%edi): same_value
87 integer reg7 (%edi): same_value
139 integer reg7 (%rsp): location expression: call_frame_cfa stack_value
205 integer reg7 (%rsp): location expression: call_frame_cfa stack_value
309 integer reg7 (r7): undefined
1331 integer reg7 (r7): undefined
2359 integer reg7 (r7): undefined
3385 integer reg7 (%r7): same_value
3462 integer reg7 (%r7): same_value
3540 integer reg7 (r7): same_value
[all …]
/external/libyuv/files/source/
Drotate_msa.cc85 v16u8 reg0, reg1, reg2, reg3, reg4, reg5, reg6, reg7; in TransposeWx16_MSA() local
109 ILVRL_H(vec0, vec2, vec1, vec3, reg4, reg5, reg6, reg7); in TransposeWx16_MSA()
111 ILVRL_W(reg2, reg6, reg3, reg7, res4, res5, res6, res7); in TransposeWx16_MSA()
131 ILVRL_H(vec0, vec2, vec1, vec3, reg4, reg5, reg6, reg7); in TransposeWx16_MSA()
147 res8 = (v16u8)__msa_ilvr_w((v4i32)reg7, (v4i32)reg3); in TransposeWx16_MSA()
148 res9 = (v16u8)__msa_ilvl_w((v4i32)reg7, (v4i32)reg3); in TransposeWx16_MSA()
166 v16u8 reg0, reg1, reg2, reg3, reg4, reg5, reg6, reg7; in TransposeUVWx16_MSA() local
190 ILVRL_H(vec0, vec2, vec1, vec3, reg4, reg5, reg6, reg7); in TransposeUVWx16_MSA()
192 ILVRL_W(reg2, reg6, reg3, reg7, res4, res5, res6, res7); in TransposeUVWx16_MSA()
212 ILVRL_H(vec0, vec2, vec1, vec3, reg4, reg5, reg6, reg7); in TransposeUVWx16_MSA()
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Drow_msa.cc826 v8u16 reg0, reg1, reg2, reg3, reg4, reg5, reg6, reg7, reg8, reg9; in ARGBToUVRow_MSA() local
899 reg7 = reg1 * const_0x70; in ARGBToUVRow_MSA()
903 reg7 += const_0x8080; in ARGBToUVRow_MSA()
917 reg7 -= reg9; in ARGBToUVRow_MSA()
921 reg7 = (v8u16)__msa_srai_h((v8i16)reg7, 8); in ARGBToUVRow_MSA()
924 dst0 = (v16u8)__msa_pckev_b((v16i8)reg7, (v16i8)reg6); in ARGBToUVRow_MSA()
1237 v4u32 reg0, reg1, reg2, reg3, reg4, reg5, reg6, reg7; in ARGBAttenuateRow_MSA() local
1267 reg7 = (v4u32)__msa_ilvl_h(zero, (v8i16)vec7); in ARGBAttenuateRow_MSA()
1275 reg7 *= (v4u32)__msa_ilvl_h(zero, (v8i16)vec3); in ARGBAttenuateRow_MSA()
1283 reg7 = (v4u32)__msa_srai_w((v4i32)reg7, 24); in ARGBAttenuateRow_MSA()
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Dscale_msa.cc133 v8u16 reg0, reg1, reg2, reg3, reg4, reg5, reg6, reg7; in ScaleARGBRowDownEvenBox_MSA() local
164 reg7 = (v8u16)__msa_pckod_d((v2i64)reg3, (v2i64)reg1); in ScaleARGBRowDownEvenBox_MSA()
166 reg5 += reg7; in ScaleARGBRowDownEvenBox_MSA()
/external/libvpx/libvpx/third_party/libyuv/source/
Drotate_msa.cc85 v16u8 reg0, reg1, reg2, reg3, reg4, reg5, reg6, reg7; in TransposeWx16_MSA() local
109 ILVRL_H(vec0, vec2, vec1, vec3, reg4, reg5, reg6, reg7); in TransposeWx16_MSA()
111 ILVRL_W(reg2, reg6, reg3, reg7, res4, res5, res6, res7); in TransposeWx16_MSA()
131 ILVRL_H(vec0, vec2, vec1, vec3, reg4, reg5, reg6, reg7); in TransposeWx16_MSA()
147 res8 = (v16u8)__msa_ilvr_w((v4i32)reg7, (v4i32)reg3); in TransposeWx16_MSA()
148 res9 = (v16u8)__msa_ilvl_w((v4i32)reg7, (v4i32)reg3); in TransposeWx16_MSA()
166 v16u8 reg0, reg1, reg2, reg3, reg4, reg5, reg6, reg7; in TransposeUVWx16_MSA() local
190 ILVRL_H(vec0, vec2, vec1, vec3, reg4, reg5, reg6, reg7); in TransposeUVWx16_MSA()
192 ILVRL_W(reg2, reg6, reg3, reg7, res4, res5, res6, res7); in TransposeUVWx16_MSA()
212 ILVRL_H(vec0, vec2, vec1, vec3, reg4, reg5, reg6, reg7); in TransposeUVWx16_MSA()
[all …]
Dscale_msa.cc141 v8u16 reg0, reg1, reg2, reg3, reg4, reg5, reg6, reg7; in ScaleARGBRowDownEvenBox_MSA() local
172 reg7 = (v8u16)__msa_pckod_d((v2i64)reg3, (v2i64)reg1); in ScaleARGBRowDownEvenBox_MSA()
174 reg5 += reg7; in ScaleARGBRowDownEvenBox_MSA()
669 v16u8 reg0, reg1, reg2, reg3, reg4, reg5, reg6, reg7; in ScaleARGBFilterCols_MSA() local
708 reg7 = (v16u8)__msa_ilvl_b((v16i8)src3, (v16i8)src1); in ScaleARGBFilterCols_MSA()
712 tmp3 = __msa_dotp_u_h(reg7, mult3); in ScaleARGBFilterCols_MSA()
767 v8i16 reg6, reg7, reg8, reg9, reg10, reg11; in ScaleRowDown34_0_Box_MSA() local
809 reg7 = (v8i16)__msa_dotp_u_h(vec7, const1); in ScaleRowDown34_0_Box_MSA()
821 reg7 = __msa_srar_h(reg7, shft1); in ScaleRowDown34_0_Box_MSA()
827 reg1 = reg1 * 3 + reg7; in ScaleRowDown34_0_Box_MSA()
[all …]
Drow_msa.cc826 v8u16 reg0, reg1, reg2, reg3, reg4, reg5, reg6, reg7, reg8, reg9; in ARGBToUVRow_MSA() local
899 reg7 = reg1 * const_0x70; in ARGBToUVRow_MSA()
903 reg7 += const_0x8080; in ARGBToUVRow_MSA()
917 reg7 -= reg9; in ARGBToUVRow_MSA()
921 reg7 = (v8u16)__msa_srai_h((v8i16)reg7, 8); in ARGBToUVRow_MSA()
924 dst0 = (v16u8)__msa_pckev_b((v16i8)reg7, (v16i8)reg6); in ARGBToUVRow_MSA()
1243 v4u32 reg0, reg1, reg2, reg3, reg4, reg5, reg6, reg7; in ARGBAttenuateRow_MSA() local
1273 reg7 = (v4u32)__msa_ilvl_h(zero, (v8i16)vec7); in ARGBAttenuateRow_MSA()
1281 reg7 *= (v4u32)__msa_ilvl_h(zero, (v8i16)vec3); in ARGBAttenuateRow_MSA()
1289 reg7 = (v4u32)__msa_srai_w((v4i32)reg7, 24); in ARGBAttenuateRow_MSA()
[all …]
/external/u-boot/board/freescale/ls1046ardb/
Dcpld.c34 u8 reg7 = CPLD_READ(vbank); in cpld_set_altbank() local
43 reg7 = (reg7 & ~CPLD_BANK_SEL_MASK) | CPLD_BANK_SEL_ALTBANK; in cpld_set_altbank()
44 CPLD_WRITE(vbank, reg7); in cpld_set_altbank()
/external/u-boot/board/freescale/ls1043ardb/
Dcpld.c34 u8 reg7 = CPLD_READ(vbank); in cpld_set_altbank() local
43 reg7 = (reg7 & ~CPLD_BANK_SEL_MASK) | CPLD_BANK_SEL_ALTBANK; in cpld_set_altbank()
44 CPLD_WRITE(vbank, reg7); in cpld_set_altbank()
/external/swiftshader/third_party/llvm-7.0/llvm/test/tools/llvm-readobj/
Dunwind.test52 CHECK-NEXT: DW_CFA_def_cfa: reg7 +8
77 CHECK-NEXT: DW_CFA_def_cfa: reg7 +8
108 CHECK-NEXT: DW_CFA_def_cfa: reg7 +8
127 CHECK-NEXT: DW_CFA_def_cfa: reg7 +8
153 CHECK-NEXT: DW_CFA_def_cfa: reg7 +8
/external/u-boot/arch/arm/lib/
Dmemcpy.S24 .macro ldr8w ptr reg1 reg2 reg3 reg4 reg5 reg6 reg7 reg8 abort
25 ldmia \ptr!, {\reg1, \reg2, \reg3, \reg4, \reg5, \reg6, \reg7, \reg8}
36 .macro str8w ptr reg1 reg2 reg3 reg4 reg5 reg6 reg7 reg8 abort
37 stmia \ptr!, {\reg1, \reg2, \reg3, \reg4, \reg5, \reg6, \reg7, \reg8}
/external/llvm/test/CodeGen/AMDGPU/
Dpv.ll6 … x float> inreg %reg4, <4 x float> inreg %reg5, <4 x float> inreg %reg6, <4 x float> inreg %reg7) {
32 %24 = extractelement <4 x float> %reg7, i32 0
33 %25 = extractelement <4 x float> %reg7, i32 1
34 %26 = extractelement <4 x float> %reg7, i32 2
35 %27 = extractelement <4 x float> %reg7, i32 3
Dbig_alu.ll5 …eg4, <4 x float> inreg %reg5, <4 x float> inreg %reg6, <4 x float> inreg %reg7, <4 x float> inreg …
49 %tmp42 = extractelement <4 x float> %reg7, i32 0
50 %tmp43 = extractelement <4 x float> %reg7, i32 1
51 %tmp44 = extractelement <4 x float> %reg7, i32 2
52 %tmp45 = extractelement <4 x float> %reg7, i32 3
/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/AMDGPU/
Dpv.ll5 … x float> inreg %reg4, <4 x float> inreg %reg5, <4 x float> inreg %reg6, <4 x float> inreg %reg7) {
31 %tmp36 = extractelement <4 x float> %reg7, i32 0
32 %tmp37 = extractelement <4 x float> %reg7, i32 1
33 %tmp38 = extractelement <4 x float> %reg7, i32 2
34 %tmp39 = extractelement <4 x float> %reg7, i32 3
Dbig_alu.ll5 …eg4, <4 x float> inreg %reg5, <4 x float> inreg %reg6, <4 x float> inreg %reg7, <4 x float> inreg …
49 %tmp42 = extractelement <4 x float> %reg7, i32 0
50 %tmp43 = extractelement <4 x float> %reg7, i32 1
51 %tmp44 = extractelement <4 x float> %reg7, i32 2
52 %tmp45 = extractelement <4 x float> %reg7, i32 3
/external/swiftshader/third_party/llvm-7.0/llvm/test/Transforms/NewGVN/
Dpr33367.ll98 %reg7 = load i64, i64* %preg7, align 8, !tbaa !26
101 %add2c279 = add i64 %reg7, %reg4
/external/vixl/src/aarch64/
Doperands-aarch64.h490 const CPURegister& reg7 = NoReg,
504 const CPURegister& reg7 = NoCPUReg,
516 const CPURegister& reg7 = NoReg,
Dassembler-aarch64.cc5942 const CPURegister& reg7, in AreAliased() argument
5950 const CPURegister regs[] = {reg1, reg2, reg3, reg4, reg5, reg6, reg7, reg8}; in AreAliased()
5981 const CPURegister& reg7, in AreSameSizeAndType() argument
5990 match &= !reg7.IsValid() || reg7.IsSameSizeAndType(reg1); in AreSameSizeAndType()
6001 const CPURegister& reg7, in AreEven() argument
6010 even &= !reg7.IsValid() || ((reg7.GetCode() % 2) == 0); in AreEven()
/external/llvm/include/llvm/Support/
DDwarf.def208 HANDLE_DW_OP(0x57, reg7)
/external/elfutils/libdw/
Dknown-dwarf.h527 DWARF_ONE_KNOWN_DW_OP (reg7, DW_OP_reg7) \
/external/v8/src/arm64/
Dassembler-arm64.cc221 const CPURegister& reg7, const CPURegister& reg8) { in AreAliased() argument
228 const CPURegister regs[] = {reg1, reg2, reg3, reg4, reg5, reg6, reg7, reg8}; in AreAliased()
258 const CPURegister& reg7, const CPURegister& reg8) { in AreSameSizeAndType() argument
266 match &= !reg7.IsValid() || reg7.IsSameSizeAndType(reg1); in AreSameSizeAndType()
/external/swiftshader/third_party/llvm-7.0/llvm/include/llvm/BinaryFormat/
DDwarf.def531 HANDLE_DW_OP(0x57, reg7, 2, DWARF)

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