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Searched refs:reg_map (Results 1 – 19 of 19) sorted by relevance

/external/pcre/dist2/src/sljit/
DsljitNativeTILEGX_64.c52 static const sljit_u8 reg_map[SLJIT_NUMBER_OF_REGISTERS + 6] = { variable
1163 FAIL_IF(ADDLI_SOLO(reg_map[dst_ar], ZERO, imm >> 48)); in emit_const_64()
1164 FAIL_IF(SHL16INSLI_SOLO(reg_map[dst_ar], reg_map[dst_ar], imm >> 32)); in emit_const_64()
1165 FAIL_IF(SHL16INSLI_SOLO(reg_map[dst_ar], reg_map[dst_ar], imm >> 16)); in emit_const_64()
1166 return SHL16INSLI_SOLO(reg_map[dst_ar], reg_map[dst_ar], imm); in emit_const_64()
1169 FAIL_IF(ADDLI(reg_map[dst_ar], ZERO, imm >> 48)); in emit_const_64()
1170 FAIL_IF(SHL16INSLI(reg_map[dst_ar], reg_map[dst_ar], imm >> 32)); in emit_const_64()
1171 FAIL_IF(SHL16INSLI(reg_map[dst_ar], reg_map[dst_ar], imm >> 16)); in emit_const_64()
1172 return SHL16INSLI(reg_map[dst_ar], reg_map[dst_ar], imm); in emit_const_64()
1209 FAIL_IF(ST_ADD(ADDR_TMP_mapped, reg_map[i], -8)); in sljit_emit_enter()
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DsljitNativeX86_32.c110 PUSH_REG(reg_map[TMP_REG1]); in sljit_emit_enter()
114 *inst++ = MOD_REG | (reg_map[TMP_REG1] << 3) | 0x4 /* esp */; in sljit_emit_enter()
118 PUSH_REG(reg_map[SLJIT_S2]); in sljit_emit_enter()
120 PUSH_REG(reg_map[SLJIT_S1]); in sljit_emit_enter()
122 PUSH_REG(reg_map[SLJIT_S0]); in sljit_emit_enter()
127 inst[1] = MOD_REG | (reg_map[SLJIT_S0] << 3) | reg_map[SLJIT_R2]; in sljit_emit_enter()
132 inst[1] = MOD_REG | (reg_map[SLJIT_S1] << 3) | reg_map[SLJIT_R1]; in sljit_emit_enter()
137 inst[1] = MOD_DISP8 | (reg_map[SLJIT_S2] << 3) | 0x4 /* esp */; in sljit_emit_enter()
144 inst[1] = MOD_DISP8 | (reg_map[SLJIT_S0] << 3) | reg_map[TMP_REG1]; in sljit_emit_enter()
150 inst[1] = MOD_DISP8 | (reg_map[SLJIT_S1] << 3) | reg_map[TMP_REG1]; in sljit_emit_enter()
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DsljitNativeX86_64.c36 *inst++ = REX_W | ((reg_map[reg] <= 7) ? 0 : REX_B); in emit_load_imm64()
37 *inst++ = MOV_r_i32 + (reg_map[reg] & 0x7); in emit_load_imm64()
47 SLJIT_ASSERT(reg_map[TMP_REG2] >= 8); in generate_far_jump_code()
101 size = reg_map[i] >= 8 ? 2 : 1; in sljit_emit_enter()
105 if (reg_map[i] >= 8) in sljit_emit_enter()
111 size = reg_map[i] >= 8 ? 2 : 1; in sljit_emit_enter()
115 if (reg_map[i] >= 8) in sljit_emit_enter()
133 inst[2] = MOD_REG | (reg_map[SLJIT_S0] << 3) | 0x7 /* rdi */; in sljit_emit_enter()
151 inst[2] = MOD_REG | (reg_map[SLJIT_S0] << 3) | 0x1 /* rcx */; in sljit_emit_enter()
157 inst[2] = MOD_REG | (reg_map[SLJIT_S1] << 3) | 0x2 /* rdx */; in sljit_emit_enter()
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DsljitNativeX86_common.c73 static const sljit_u8 reg_map[SLJIT_NUMBER_OF_REGISTERS + 3] = { variable
98 static const sljit_u8 reg_map[SLJIT_NUMBER_OF_REGISTERS + 4] = { variable
107 static const sljit_u8 reg_map[SLJIT_NUMBER_OF_REGISTERS + 4] = { variable
695 return emit_do_imm(compiler, MOV_r_i32 + reg_map[dst], srcw); in emit_mov()
702 … return emit_do_imm32(compiler, (reg_map[dst] >= 8) ? REX_B : 0, MOV_r_i32 + reg_lmap[dst], srcw); in emit_mov()
771 reg_map[SLJIT_R0] == 0 in sljit_emit_op0()
772 && reg_map[SLJIT_R1] == 2 in sljit_emit_op0()
773 && reg_map[TMP_REG1] > 7); in sljit_emit_op0()
776 reg_map[SLJIT_R0] == 0 in sljit_emit_op0()
777 && reg_map[SLJIT_R1] < 7 in sljit_emit_op0()
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DsljitNativeARM_T2_32.c48 static const sljit_u8 reg_map[SLJIT_NUMBER_OF_REGISTERS + 5] = { variable
60 #define RD3(rd) (reg_map[rd])
61 #define RN3(rn) (reg_map[rn] << 3)
62 #define RM3(rm) (reg_map[rm] << 6)
63 #define RDN3(rdn) (reg_map[rdn] << 8)
69 ((reg_map[rn] << 3) | (reg_map[rd] & 0x7) | ((reg_map[rd] & 0x8) << 4))
71 (reg_map[reg1] <= 7 && reg_map[reg2] <= 7)
73 (reg_map[reg1] <= 7 && reg_map[reg2] <= 7 && reg_map[reg3] <= 7)
76 #define RD4(rd) (reg_map[rd] << 8)
77 #define RN4(rn) (reg_map[rn] << 16)
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DsljitNativeARM_32.c63 static const sljit_u8 reg_map[SLJIT_NUMBER_OF_REGISTERS + 5] = { variable
71 #define RM(rm) (reg_map[rm])
72 #define RD(rd) (reg_map[rd] << 12)
73 #define RN(rn) (reg_map[rn] << 16)
273 SLJIT_ASSERT(reg_map[TMP_REG1] != 14); in emit_blx()
923 push |= 1 << reg_map[i]; in sljit_emit_enter()
926 push |= 1 << reg_map[i]; in sljit_emit_enter()
983 pop |= 1 << reg_map[i]; in sljit_emit_return()
986 pop |= 1 << reg_map[i]; in sljit_emit_return()
1024 …(reg_map[(flags & ARGS_SWAPPED) ? src1 : src2] << 8) | (opcode << 5) | 0x10 | RM((flags & ARGS_SWA…
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DsljitNativeARM_64.c46 static const sljit_u8 reg_map[SLJIT_NUMBER_OF_REGISTERS + 8] = { variable
55 #define RD(rd) (reg_map[rd])
56 #define RT(rt) (reg_map[rt])
57 #define RN(rn) (reg_map[rn] << 5)
58 #define RT2(rt2) (reg_map[rt2] << 10)
59 #define RM(rm) (reg_map[rm] << 16)
1127 SLJIT_ASSERT(reg_map[1] == 0 && reg_map[3] == 2 && reg_map[5] == 4); in sljit_emit_op1()
1284 return reg_map[reg]; in sljit_get_register_index()
DsljitNativeSPARC_common.c100 static const sljit_u8 reg_map[SLJIT_NUMBER_OF_REGISTERS + 6] = { variable
112 #define D(d) (reg_map[d] << 25)
116 #define S1(s1) (reg_map[s1] << 14)
119 #define S2(s2) (reg_map[s2])
127 #define DR(dr) (reg_map[dr])
947 return reg_map[reg]; in sljit_get_register_index()
DsljitNativePPC_common.c107 static const sljit_u8 reg_map[SLJIT_NUMBER_OF_REGISTERS + 7] = { variable
118 #define D(d) (reg_map[d] << 21)
119 #define S(s) (reg_map[s] << 21)
120 #define A(a) (reg_map[a] << 16)
121 #define B(b) (reg_map[b] << 11)
122 #define C(c) (reg_map[c] << 6)
1455 return reg_map[reg]; in sljit_get_register_index()
DsljitNativeMIPS_common.c66 static const sljit_u8 reg_map[SLJIT_NUMBER_OF_REGISTERS + 5] = { variable
88 #define S(s) (reg_map[s] << 21)
89 #define T(t) (reg_map[t] << 16)
90 #define D(d) (reg_map[d] << 11)
101 #define DR(dr) (reg_map[dr])
1286 return reg_map[reg]; in sljit_get_register_index()
DsljitNativeSPARC_32.c153 reg = reg_map[*src & REG_MASK]; in call_with_args()
DsljitNativeMIPS_32.c451 SLJIT_ASSERT(reg_map[TMP_REG1] == 4 && freg_map[TMP_FREG1] == 12); in call_with_args()
DsljitNativeMIPS_64.c550 SLJIT_ASSERT(reg_map[TMP_REG1] == 4 && freg_map[TMP_FREG1] == 12); in call_with_args()
/external/mesa3d/src/gallium/drivers/vc5/
Dv3dx_simulator.c105 static const uint32_t reg_map[] = { in v3dX() local
115 if (args->param < ARRAY_SIZE(reg_map) && reg_map[args->param]) { in v3dX()
116 args->value = V3D_READ(reg_map[args->param]); in v3dX()
/external/u-boot/include/
Dddr_spd.h384 u8 reg_map; member
410 uint8_t reg_map; member
/external/u-boot/drivers/ddr/marvell/a38x/
Dddr3_training_bist.c227 u16 *reg_map = ddr3_tip_get_mask_results_pup_reg_map(); in mv_ddr_tip_bist() local
236 ddr3_tip_if_read(0, ACCESS_TYPE_UNICAST, 0, reg_map[subphy], &read_data, MASK_ALL_BITS); in mv_ddr_tip_bist()
/external/u-boot/drivers/ddr/fsl/
Dddr4_dimm_params.c192 if (spd->mod_section.registered.reg_map & 0x1) in ddr_compute_dimm_parameters()
Dinteractive.c1581 PRINT_NXS(136, spd->mod_section.registered.reg_map, in ddr4_spd_dump()
1603 PRINT_NXS(136, spd->mod_section.loadreduced.reg_map, in ddr4_spd_dump()
/external/u-boot/arch/arm/mach-exynos/
Dclock.c1049 const int reg_map[] = {0, CPLL, DPLL, MPLL, SPLL, IPLL, EPLL, in exynos5800_get_lcd_clk() local
1051 sclk = get_pll_clk(reg_map[sel]); in exynos5800_get_lcd_clk()