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Searched refs:reg_offset (Results 1 – 25 of 42) sorted by relevance

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/external/u-boot/drivers/power/pmic/
Dpmic_tps65910.c43 unsigned int reg_offset; in tps65910_voltage_update() local
47 reg_offset = TPS65910_VDD1_OP_REG; in tps65910_voltage_update()
49 reg_offset = TPS65910_VDD2_OP_REG; in tps65910_voltage_update()
52 ret = i2c_read(TPS65910_CTRL_I2C_ADDR, reg_offset, 1, &buf, 1); in tps65910_voltage_update()
58 ret = i2c_write(TPS65910_CTRL_I2C_ADDR, reg_offset, 1, &buf, 1); in tps65910_voltage_update()
63 ret = i2c_read(TPS65910_CTRL_I2C_ADDR, reg_offset, 1, &buf, 1); in tps65910_voltage_update()
70 ret = i2c_write(TPS65910_CTRL_I2C_ADDR, reg_offset, 1, &buf, 1); in tps65910_voltage_update()
74 ret = i2c_read(TPS65910_CTRL_I2C_ADDR, reg_offset, 1, &buf, 1); in tps65910_voltage_update()
/external/u-boot/arch/powerpc/include/asm/
Dfsl_liodn.h14 unsigned long reg_offset[2]; member
20 .reg_offset[0] = offsetof(ccsr_gur_t, rio##port##liodnr) \
26 .reg_offset[0] = offsetof(ccsr_gur_t, rio##port##liodnr) \
28 .reg_offset[1] = offsetof(ccsr_gur_t, rio##port##maintliodnr) \
34 .reg_offset[0] = offsetof(struct ccsr_rio, liodn) \
44 unsigned long reg_offset; member
56 unsigned long reg_offset; member
73 .reg_offset = off + CONFIG_SYS_CCSRBAR, \
80 .reg_offset = off + CONFIG_SYS_CCSRBAR, \
87 .reg_offset = off + CONFIG_SYS_CCSRBAR, \
/external/mesa3d/src/intel/compiler/
Dbrw_ir_fs.h180 reg_offset(const fs_reg &r) in reg_offset() function
223 !(reg_offset(r) + dr <= reg_offset(s) || in regions_overlap()
224 reg_offset(s) + ds <= reg_offset(r)); in regions_overlap()
237 reg_offset(r) >= reg_offset(s) && in region_contained_in()
238 reg_offset(r) + dr <= reg_offset(s) + ds; in region_contained_in()
426 return DIV_ROUND_UP(reg_offset(inst->dst) % REG_SIZE + in regs_written()
443 return DIV_ROUND_UP(reg_offset(inst->src[i]) % reg_size + in regs_read()
Dbrw_ir_vec4.h231 reg_offset(const backend_reg &r) in reg_offset() function
263 !(reg_offset(r) + dr <= reg_offset(s) || in regions_overlap()
264 reg_offset(s) + ds <= reg_offset(r)); in regions_overlap()
416 return DIV_ROUND_UP(reg_offset(inst->dst) % REG_SIZE + inst->size_written, in regs_written()
431 return DIV_ROUND_UP(reg_offset(inst->src[i]) % reg_size + inst->size_read(i), in regs_read()
Dbrw_vec4_visitor.cpp1428 src_reg *reladdr, int reg_offset) in get_scratch_offset() argument
1450 brw_imm_d(reg_offset))); in get_scratch_offset()
1457 brw_imm_d(reg_offset * message_header_scale))); in get_scratch_offset()
1461 return brw_imm_d(reg_offset * message_header_scale); in get_scratch_offset()
1477 int reg_offset = base_offset + orig_src.offset / REG_SIZE; in emit_scratch_read() local
1479 reg_offset); in emit_scratch_read()
1487 index = get_scratch_offset(block, inst, orig_src.reladdr, reg_offset + 1); in emit_scratch_read()
1506 int reg_offset = base_offset + inst->dst.offset / REG_SIZE; in emit_scratch_write() local
1508 reg_offset); in emit_scratch_write()
1564 reg_offset + 1); in emit_scratch_write()
[all …]
/external/u-boot/board/siemens/pxm2/
Dboard.c94 unsigned int reg_offset; in voltage_update() local
97 reg_offset = PMIC_VDD1_OP_REG; in voltage_update()
99 reg_offset = PMIC_VDD2_OP_REG; in voltage_update()
102 if (i2c_read(PMIC_CTRL_I2C_ADDR, reg_offset, 1, buf, 1)) in voltage_update()
107 if (i2c_write(PMIC_CTRL_I2C_ADDR, reg_offset, 1, buf, 1)) in voltage_update()
111 if (i2c_read(PMIC_CTRL_I2C_ADDR, reg_offset, 1, buf, 1)) in voltage_update()
117 if (i2c_write(PMIC_CTRL_I2C_ADDR, reg_offset, 1, buf, 1)) in voltage_update()
120 if (i2c_read(PMIC_CTRL_I2C_ADDR, reg_offset, 1, buf, 1)) in voltage_update()
/external/u-boot/drivers/pinctrl/mvebu/
Dpinctrl-mvebu.c98 int reg_offset; in mvebu_pinctrl_set_state() local
109 reg_offset = priv->reg_direction * 4 * in mvebu_pinctrl_set_state()
113 clrsetbits_le32(priv->base_reg + reg_offset, in mvebu_pinctrl_set_state()
155 int reg_offset; in mvebu_pinctrl_set_state_all() local
170 reg_offset = priv->reg_direction * 4 * in mvebu_pinctrl_set_state_all()
174 clrsetbits_le32(priv->base_reg + reg_offset, in mvebu_pinctrl_set_state_all()
/external/u-boot/drivers/reset/
Dreset-meson.c40 uint reg_offset = LEVEL_OFFSET + (bank << 2); in meson_reset_level() local
43 regmap_read(priv->regmap, reg_offset, &val); in meson_reset_level()
48 regmap_write(priv->regmap, reg_offset, val); in meson_reset_level()
Dreset-rockchip.c106 int rockchip_reset_bind(struct udevice *pdev, u32 reg_offset, u32 reg_number) in rockchip_reset_bind() argument
119 priv->reset_reg_offset = reg_offset; in rockchip_reset_bind()
/external/u-boot/arch/arm/include/asm/arch-ls102xa/
Dls102xa_stream_id.h14 .reg_offset = off + CONFIG_SYS_IMMR, \
21 .reg_offset = off + CONFIG_SYS_IMMR, \
62 unsigned long reg_offset; member
/external/u-boot/drivers/pinctrl/broadcom/
Dpinctrl-bcm283x.c35 int reg_offset; in bcm2835_gpio_set_func_id() local
38 reg_offset = BCM2835_GPIO_FSEL_BANK(gpio); in bcm2835_gpio_set_func_id()
41 clrsetbits_le32(&priv->base_reg[reg_offset], in bcm2835_gpio_set_func_id()
/external/u-boot/arch/arm/mach-omap2/am33xx/
Dmux.c31 for (i = 0; mod_pin_mux[i].reg_offset != -1; i++) in configure_module_pin_mux()
32 MUX_CFG(mod_pin_mux[i].val, mod_pin_mux[i].reg_offset); in configure_module_pin_mux()
/external/u-boot/drivers/gpio/
Dgpio-uniphier.c86 unsigned int bank, reg_offset; in uniphier_gpio_offset_read() local
90 reg_offset = uniphier_gpio_bank_to_reg(bank) + reg; in uniphier_gpio_offset_read()
92 return !!(readl(priv->regs + reg_offset) & mask); in uniphier_gpio_offset_read()
Dzynq_gpio.c222 unsigned int reg_offset, bank_num, bank_pin_num; in zynq_gpio_set_value() local
233 reg_offset = ZYNQ_GPIO_DATA_MSW_OFFSET(bank_num); in zynq_gpio_set_value()
235 reg_offset = ZYNQ_GPIO_DATA_LSW_OFFSET(bank_num); in zynq_gpio_set_value()
246 writel(value, priv->base + reg_offset); in zynq_gpio_set_value()
/external/u-boot/arch/powerpc/cpu/mpc85xx/
Dliodn.c32 unsigned long reg_off = tbl[i].reg_offset[0]; in set_srio_liodn()
36 reg_off = tbl[i].reg_offset[1]; in set_srio_liodn()
55 out_be32((volatile u32 *)(tbl[i].reg_offset), liodn); in set_liodn()
71 out_be32((volatile u32 *)(tbl[i].reg_offset), liodn); in set_fman_liodn()
163 out_be32((u32 *)(tbl[i].reg_offset), tbl[i].id[0]); in set_rman_liodn()
/external/u-boot/drivers/ddr/marvell/a38x/
Dddr3_training_ip_engine.c701 u32 reg_offset, pup_cnt, start_pup, end_pup, start_reg, end_reg; in ddr3_tip_read_training_result() local
787 for (reg_offset = start_reg; reg_offset <= end_reg; in ddr3_tip_read_training_result()
788 reg_offset++) { in ddr3_tip_read_training_result()
795 reg_addr[reg_offset], in ddr3_tip_read_training_result()
802 [reg_offset] = in ddr3_tip_read_training_result()
807 [reg_offset] = in ddr3_tip_read_training_result()
813 interface_train_res[reg_offset] in ddr3_tip_read_training_result()
820 reg_offset, in ddr3_tip_read_training_result()
822 [reg_offset], in ddr3_tip_read_training_result()
824 [reg_offset])); in ddr3_tip_read_training_result()
/external/u-boot/drivers/net/
Dmvgbe.c325 u32 reg_offset; in port_uc_addr() local
332 reg_offset = uc_nibble % 4; in port_uc_addr()
341 unicast_reg &= (0xFF << (8 * reg_offset)); in port_uc_addr()
347 unicast_reg &= (0xFF << (8 * reg_offset)); in port_uc_addr()
348 unicast_reg |= ((0x01 | (RXUQ << 1)) << (8 * reg_offset)); in port_uc_addr()
Dsh_eth.h606 const u16 *reg_offset = sh_eth_offset_gigabit; in sh_eth_reg_addr() local
608 const u16 *reg_offset = sh_eth_offset_fast_sh4; in sh_eth_reg_addr()
612 return (unsigned long)port->iobase + reg_offset[enum_index]; in sh_eth_reg_addr()
/external/mesa3d/src/amd/vulkan/winsys/amdgpu/
Dradv_amdgpu_winsys.c130 unsigned reg_offset, in radv_amdgpu_winsys_read_registers() argument
135 return amdgpu_read_mm_registers(ws->dev, reg_offset / 4, num_registers, in radv_amdgpu_winsys_read_registers()
/external/u-boot/arch/arm/include/asm/arch-am33xx/
Dmux.h33 short reg_offset; member
/external/u-boot/drivers/serial/
Dns16550.c106 serial_out_shift(addr + plat->reg_offset, plat->reg_shift, value); in ns16550_writeb()
117 return serial_in_shift(addr + plat->reg_offset, plat->reg_shift); in ns16550_readb()
436 plat->reg_offset = dev_read_u32_default(dev, "reg-offset", 0); in ns16550_serial_ofdata_to_platdata()
Dserial_intel_mid.c31 writel(value, addr + plat->reg_offset); in mid_writel()
/external/u-boot/board/freescale/common/
Dls102xa_stream_id.c33 out_le32((u32 *)(tbl[i].reg_offset), liodn); in ls1021x_config_caam_stream_id()
/external/u-boot/arch/arm/include/asm/arch-rockchip/
Dclock.h95 int rockchip_reset_bind(struct udevice *pdev, u32 reg_offset, u32 reg_number);
/external/mesa3d/src/gallium/drivers/r600/
Deg_debug.c134 unsigned reg_offset) in ac_parse_set_reg_packet() argument
136 unsigned reg = (ib[1] << 2) + reg_offset; in ac_parse_set_reg_packet()

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