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/external/deqp-deps/glslang/Test/baseResults/
Dspv.vulkan100.subgroupPartitioned.comp.out2 ERROR: 0:19: 'subgroup op' : requires SPIR-V 1.3
3 ERROR: 0:21: 'subgroup op' : requires SPIR-V 1.3
4 ERROR: 0:22: 'subgroup op' : requires SPIR-V 1.3
5 ERROR: 0:23: 'subgroup op' : requires SPIR-V 1.3
6 ERROR: 0:24: 'subgroup op' : requires SPIR-V 1.3
7 ERROR: 0:26: 'subgroup op' : requires SPIR-V 1.3
8 ERROR: 0:27: 'subgroup op' : requires SPIR-V 1.3
9 ERROR: 0:28: 'subgroup op' : requires SPIR-V 1.3
10 ERROR: 0:29: 'subgroup op' : requires SPIR-V 1.3
11 ERROR: 0:31: 'subgroup op' : requires SPIR-V 1.3
[all …]
Dspv.vulkan100.subgroupArithmetic.comp.out2 ERROR: 0:19: 'subgroup op' : requires SPIR-V 1.3
3 ERROR: 0:20: 'subgroup op' : requires SPIR-V 1.3
4 ERROR: 0:21: 'subgroup op' : requires SPIR-V 1.3
5 ERROR: 0:22: 'subgroup op' : requires SPIR-V 1.3
6 ERROR: 0:24: 'subgroup op' : requires SPIR-V 1.3
7 ERROR: 0:25: 'subgroup op' : requires SPIR-V 1.3
8 ERROR: 0:26: 'subgroup op' : requires SPIR-V 1.3
9 ERROR: 0:27: 'subgroup op' : requires SPIR-V 1.3
10 ERROR: 0:29: 'subgroup op' : requires SPIR-V 1.3
11 ERROR: 0:30: 'subgroup op' : requires SPIR-V 1.3
[all …]
/external/llvm/test/MC/ARM/
Dfullfp16-neon-neg.s8 @ CHECK: error: instruction requires:
9 @ CHECK: error: instruction requires:
13 @ CHECK: error: instruction requires:
14 @ CHECK: error: instruction requires:
18 @ CHECK: error: instruction requires:
19 @ CHECK: error: instruction requires:
23 @ CHECK: error: instruction requires:
24 @ CHECK: error: instruction requires:
28 @ CHECK: error: instruction requires:
29 @ CHECK: error: instruction requires:
[all …]
Dfullfp16-neg.s5 @ CHECK: error: instruction requires:
8 @ CHECK: error: instruction requires:
11 @ CHECK: error: instruction requires:
14 @ CHECK: error: instruction requires:
17 @ CHECK: error: instruction requires:
20 @ CHECK: error: instruction requires:
23 @ CHECK: error: instruction requires:
26 @ CHECK: error: instruction requires:
29 @ CHECK: error: instruction requires:
32 @ CHECK: error: instruction requires:
[all …]
Ddirective-arch_extension-fp.s20 @ CHECK-V7: error: instruction requires: FPARMv8
23 @ CHECK-V7: error: instruction requires: FPARMv8
25 @ CHECK-V7: error: instruction requires: FPARMv8
27 @ CHECK-V7: error: instruction requires: FPARMv8
29 @ CHECK-V7: error: instruction requires: FPARMv8
31 @ CHECK-V7: error: instruction requires: FPARMv8
33 @ CHECK-V7: error: instruction requires: FPARMv8
36 @ CHECK-V7: error: instruction requires: FPARMv8
38 @ CHECK-V7: error: instruction requires: FPARMv8
40 @ CHECK-V7: error: instruction requires: FPARMv8
[all …]
Ddirective-arch_extension-simd.s20 @ CHECK-V7: error: instruction requires: FPARMv8
22 @ CHECK-V7: error: instruction requires: FPARMv8
25 @ CHECK-V7: error: instruction requires: FPARMv8
27 @ CHECK-V7: error: instruction requires: FPARMv8
30 @ CHECK-V7: error: instruction requires: FPARMv8
32 @ CHECK-V7: error: instruction requires: FPARMv8
34 @ CHECK-V7: error: instruction requires: FPARMv8
36 @ CHECK-V7: error: instruction requires: FPARMv8
38 @ CHECK-V7: error: instruction requires: FPARMv8
40 @ CHECK-V7: error: instruction requires: FPARMv8
[all …]
Ddirective-arch_extension-crypto.s20 @ CHECK-V7: error: instruction requires: crypto armv8
23 @ CHECK-V7: error: instruction requires: crypto armv8
25 @ CHECK-V7: error: instruction requires: crypto armv8
27 @ CHECK-V7: error: instruction requires: crypto armv8
29 @ CHECK-V7: error: instruction requires: crypto armv8
32 @ CHECK-V7: error: instruction requires: crypto armv8
34 @ CHECK-V7: error: instruction requires: crypto armv8
36 @ CHECK-V7: error: instruction requires: crypto armv8
39 @ CHECK-V7: error: instruction requires: crypto armv8
41 @ CHECK-V7: error: instruction requires: crypto armv8
[all …]
/external/swiftshader/third_party/llvm-7.0/llvm/test/MC/ARM/
Ddirective-arch_extension-fp.s20 @ CHECK-V7: instruction requires: FPARMv8
23 @ CHECK-V7: instruction requires: FPARMv8
25 @ CHECK-V7: instruction requires: FPARMv8
27 @ CHECK-V7: instruction requires: FPARMv8
29 @ CHECK-V7: instruction requires: FPARMv8
31 @ CHECK-V7: instruction requires: FPARMv8
33 @ CHECK-V7: instruction requires: FPARMv8
36 @ CHECK-V7: instruction requires: FPARMv8
38 @ CHECK-V7: instruction requires: FPARMv8
40 @ CHECK-V7: instruction requires: FPARMv8
[all …]
Dfullfp16-neon-neg.s8 @ CHECK: instruction requires: {{full half-float|NEON}}
9 @ CHECK: instruction requires: {{full half-float|NEON}}
13 @ CHECK: instruction requires: {{full half-float|NEON}}
14 @ CHECK: instruction requires: {{full half-float|NEON}}
18 @ CHECK: instruction requires: {{full half-float|NEON}}
19 @ CHECK: instruction requires: {{full half-float|NEON}}
23 @ CHECK: instruction requires: {{full half-float|NEON}}
24 @ CHECK: instruction requires: {{full half-float|NEON}}
28 @ CHECK: instruction requires: {{full half-float|NEON}}
29 @ CHECK: instruction requires: {{full half-float|NEON}}
[all …]
Ddirective-arch_extension-simd.s20 @ CHECK-V7: error: instruction requires: FPARMv8
22 @ CHECK-V7: error: instruction requires: FPARMv8
25 @ CHECK-V7: error: instruction requires: FPARMv8
27 @ CHECK-V7: error: instruction requires: FPARMv8
30 @ CHECK-V7: error: instruction requires: FPARMv8
32 @ CHECK-V7: error: instruction requires: FPARMv8
34 @ CHECK-V7: error: instruction requires: FPARMv8
36 @ CHECK-V7: error: instruction requires: FPARMv8
38 @ CHECK-V7: error: instruction requires: FPARMv8
40 @ CHECK-V7: error: instruction requires: FPARMv8
[all …]
Dfullfp16-neg.s5 @ CHECK: instruction requires: full half-float
8 @ CHECK: instruction requires: full half-float
11 @ CHECK: instruction requires: full half-float
14 @ CHECK: instruction requires: full half-float
17 @ CHECK: instruction requires: full half-float
20 @ CHECK: instruction requires: full half-float
23 @ CHECK: instruction requires: full half-float
26 @ CHECK: instruction requires: full half-float
29 @ CHECK: instruction requires: full half-float
32 @ CHECK: instruction requires: full half-float
[all …]
Ddirective-arch_extension-crypto.s20 @ CHECK-V7: error: instruction requires: crypto armv8
23 @ CHECK-V7: error: instruction requires: crypto armv8
25 @ CHECK-V7: error: instruction requires: crypto armv8
27 @ CHECK-V7: error: instruction requires: crypto armv8
29 @ CHECK-V7: error: instruction requires: crypto armv8
32 @ CHECK-V7: error: instruction requires: crypto armv8
34 @ CHECK-V7: error: instruction requires: crypto armv8
36 @ CHECK-V7: error: instruction requires: crypto armv8
39 @ CHECK-V7: error: instruction requires: crypto armv8
41 @ CHECK-V7: error: instruction requires: crypto armv8
[all …]
/external/llvm/test/MC/SystemZ/
Dinsn-bad-zEC12.s5 #CHECK: error: {{(instruction requires: vector)?}}
91 #CHECK: error: {{(instruction requires: vector)?}}
93 #CHECK: error: {{(instruction requires: vector)?}}
95 #CHECK: error: {{(instruction requires: vector)?}}
97 #CHECK: error: {{(instruction requires: vector)?}}
99 #CHECK: error: {{(instruction requires: vector)?}}
108 #CHECK: error: {{(instruction requires: vector)?}}
110 #CHECK: error: {{(instruction requires: vector)?}}
112 #CHECK: error: {{(instruction requires: vector)?}}
114 #CHECK: error: {{(instruction requires: vector)?}}
[all …]
/external/clang/test/Parser/
Dcxx-concepts-requires-clause.cpp6 template <typename T> requires true
10 template <typename T> requires !0
17 template <typename> requires true
20 template <typename> requires true
23 template <typename> requires true
26 template <typename TT> requires true
30 template <typename T> requires !0
33 template <typename T> requires !0
36 template <typename T> requires !0
39 template <typename T> requires !0
[all …]
/external/swiftshader/third_party/llvm-7.0/llvm/test/MC/SystemZ/
Dinsn-bad-zEC12.s65 #CHECK: error: instruction requires: dfp-packed-conversion
155 #CHECK: error: instruction requires: dfp-packed-conversion
160 #CHECK: error: instruction requires: dfp-packed-conversion
179 #CHECK: error: instruction requires: dfp-packed-conversion
303 #CHECK: error: instruction requires: vector
340 #CHECK: error: instruction requires: load-store-on-cond-2
345 #CHECK: error: instruction requires: load-store-on-cond-2
380 #CHECK: error: instruction requires: message-security-assist-extension5
450 #CHECK: error: instruction requires: vector
452 #CHECK: error: instruction requires: vector
[all …]
/external/swiftshader/third_party/llvm-7.0/llvm/test/MC/Mips/
Dtarget-soft-float.s12 # 64: :[[@LINE-1]]:3: error: instruction requires a CPU feature not currently enabled
14 # 64: :[[@LINE-1]]:3: error: instruction requires a CPU feature not currently enabled
17 # R2: :[[@LINE-1]]:3: error: instruction requires a CPU feature not currently enabled
19 # R2: :[[@LINE-1]]:3: error: instruction requires a CPU feature not currently enabled
21 # R2: :[[@LINE-1]]:3: error: instruction requires a CPU feature not currently enabled
23 # R2: :[[@LINE-1]]:3: error: instruction requires a CPU feature not currently enabled
25 # R2: :[[@LINE-1]]:3: error: instruction requires a CPU feature not currently enabled
27 # R2: :[[@LINE-1]]:3: error: instruction requires a CPU feature not currently enabled
29 # R2: :[[@LINE-1]]:3: error: instruction requires a CPU feature not currently enabled
31 # R2: :[[@LINE-1]]:3: error: instruction requires a CPU feature not currently enabled
[all …]
/external/llvm/test/MC/Mips/
Dtarget-soft-float.s12 # 64: :[[@LINE-1]]:3: error: instruction requires a CPU feature not currently enabled
14 # 64: :[[@LINE-1]]:3: error: instruction requires a CPU feature not currently enabled
17 # R2: :[[@LINE-1]]:3: error: instruction requires a CPU feature not currently enabled
19 # R2: :[[@LINE-1]]:3: error: instruction requires a CPU feature not currently enabled
21 # R2: :[[@LINE-1]]:3: error: instruction requires a CPU feature not currently enabled
23 # R2: :[[@LINE-1]]:3: error: instruction requires a CPU feature not currently enabled
25 # R2: :[[@LINE-1]]:3: error: instruction requires a CPU feature not currently enabled
27 # R2: :[[@LINE-1]]:3: error: instruction requires a CPU feature not currently enabled
29 # R2: :[[@LINE-1]]:3: error: instruction requires a CPU feature not currently enabled
31 # R2: :[[@LINE-1]]:3: error: instruction requires a CPU feature not currently enabled
[all …]
/external/llvm/test/MC/Mips/mips32r2/
Dinvalid-dspr2.s8 …absq_s.ph $8,$a0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU f…
9 …absq_s.qb $15,$s1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU f…
10 …absq_s.w $s3,$ra # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU f…
11 …addq.ph $s1,$15,$at # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU f…
12 …addq_s.ph $s3,$s6,$s2 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU f…
13 …addq_s.w $a2,$8,$at # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU f…
14 …addqh.ph $s4,$14,$s1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU f…
15 …addqh_r.ph $sp,$25,$s8 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU f…
16 …addsc $s8,$15,$12 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU f…
17 …addu.ph $a2,$14,$s3 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU f…
[all …]
Dinvalid-dsp.s8 …absq_s.ph $8,$a0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU fe…
9 …absq_s.w $s3,$ra # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU fe…
10 …addq.ph $s1,$15,$at # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU fe…
11 …addq_s.ph $s3,$s6,$s2 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU fe…
12 …addq_s.w $a2,$8,$at # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU fe…
13 …addsc $s8,$15,$12 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU fe…
14 …addu.qb $s6,$v1,$v1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU fe…
15 …addu_s.qb $s4,$s8,$s1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU fe…
16 …addwc $k0,$s6,$s7 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU fe…
17 …bitrev $14,$at # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU fe…
[all …]
/external/swiftshader/third_party/llvm-7.0/llvm/test/MC/Mips/mips32r2/
Dinvalid-dspr2.s8 …absq_s.ph $8,$a0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU f…
9 …absq_s.qb $15,$s1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU f…
10 …absq_s.w $s3,$ra # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU f…
11 …addq.ph $s1,$15,$at # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU f…
12 …addq_s.ph $s3,$s6,$s2 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU f…
13 …addq_s.w $a2,$8,$at # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU f…
14 …addqh.ph $s4,$14,$s1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU f…
15 …addqh_r.ph $sp,$25,$s8 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU f…
16 …addsc $s8,$15,$12 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU f…
17 …addu.ph $a2,$14,$s3 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU f…
[all …]
Dinvalid-dsp.s8 …absq_s.ph $8,$a0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU fe…
9 …absq_s.w $s3,$ra # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU fe…
10 …addq.ph $s1,$15,$at # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU fe…
11 …addq_s.ph $s3,$s6,$s2 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU fe…
12 …addq_s.w $a2,$8,$at # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU fe…
13 …addsc $s8,$15,$12 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU fe…
14 …addu.qb $s6,$v1,$v1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU fe…
15 …addu_s.qb $s4,$s8,$s1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU fe…
16 …addwc $k0,$s6,$s7 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU fe…
17 …bitrev $14,$at # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU fe…
[all …]
/external/swiftshader/third_party/llvm-7.0/llvm/test/MC/Mips/mips1/
Dinvalid-mips5.s10 …ceil.l.d $f1,$f3 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feat…
11 …ceil.l.s $f18,$f13 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feat…
12 …ceil.w.d $f11,$f25 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feat…
13 …ceil.w.s $f6,$f20 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feat…
14 …cvt.d.l $f4,$f16 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feat…
15 …cvt.l.d $f24,$f15 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feat…
16 …cvt.l.s $f11,$f29 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feat…
17 …cvt.s.l $f15,$f30 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feat…
18 …dadd $s3,$at,$ra # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feat…
19 …daddi $sp,$s4,-27705 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feat…
[all …]
Dinvalid-mips4.s10 …ceil.l.d $f1,$f3 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feat…
11 …ceil.l.s $f18,$f13 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feat…
12 …ceil.w.d $f11,$f25 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feat…
13 …ceil.w.s $f6,$f20 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feat…
14 …cvt.d.l $f4,$f16 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feat…
15 …cvt.l.d $f24,$f15 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feat…
16 …cvt.l.s $f11,$f29 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feat…
17 …cvt.s.l $f15,$f30 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feat…
18 …dadd $s3,$at,$ra # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feat…
19 …daddi $sp,$s4,-27705 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feat…
[all …]
Dinvalid-mips3.s8 …dmult $s7,$9 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feat…
9 …dsub $a3,$s6,$8 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feat…
10 …ceil.l.d $f1,$f3 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feat…
11 …ceil.l.s $f18,$f13 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feat…
12 …ceil.w.d $f11,$f25 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feat…
13 …ceil.w.s $f6,$f20 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feat…
14 …cvt.d.l $f4,$f16 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feat…
15 …cvt.l.d $f24,$f15 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feat…
16 …cvt.l.s $f11,$f29 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feat…
17 …cvt.s.l $f15,$f30 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feat…
[all …]
/external/swiftshader/third_party/llvm-7.0/llvm/test/MC/Mips/mips2/
Dinvalid-mips4.s10 …ceil.l.d $f1,$f3 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU featur…
11 …ceil.l.s $f18,$f13 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU featur…
12 …cvt.d.l $f4,$f16 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU featur…
13 …cvt.l.d $f24,$f15 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU featur…
14 …cvt.l.s $f11,$f29 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU featur…
15 …cvt.s.l $f15,$f30 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU featur…
16 …dadd $s3,$at,$ra # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU featur…
17 …daddi $sp,$s4,-27705 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU featur…
18 …daddiu $k0,$s6,-4586 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU featur…
19 …daddu $s3,$at,$ra # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU featur…
[all …]

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