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/external/u-boot/arch/arm/mach-sunxi/
Drsb.c43 struct sunxi_rsb_reg * const rsb = in rsb_set_clk() local
54 writel((cd_odly << 8) | div, &rsb->ccr); in rsb_set_clk()
59 struct sunxi_rsb_reg * const rsb = in rsb_init() local
68 writel(RSB_CTRL_SOFT_RST, &rsb->ctrl); in rsb_init()
76 struct sunxi_rsb_reg * const rsb = in rsb_await_trans() local
83 stat = readl(&rsb->stat); in rsb_await_trans()
101 writel(stat, &rsb->stat); /* Clear status bits */ in rsb_await_trans()
108 struct sunxi_rsb_reg * const rsb = in rsb_set_device_mode() local
113 &rsb->dmcr); in rsb_set_device_mode()
115 while (readl(&rsb->dmcr) & RSB_DMCR_DEVICE_MODE_START) { in rsb_set_device_mode()
[all …]
/external/swiftshader/third_party/LLVM/test/CodeGen/Thumb2/
Dthumb2-rsb2.ll9 ; CHECK: rsb.w r0, r0, #171
17 ; CHECK: rsb.w r0, r0, #1179666
25 ; CHECK: rsb.w r0, r0, #872428544
33 ; CHECK: rsb.w r0, r0, #1448498774
41 ; CHECK: rsb.w r0, r0, #66846720
Dthumb2-rsb.ll9 ; CHECK: rsb r0, r0, r1, lsl #5
17 ; CHECK: rsb r0, r0, r1, lsr #6
25 ; CHECK: rsb r0, r0, r1, asr #7
35 ; CHECK: rsb r0, r0, r0, ror #8
/external/llvm/test/CodeGen/Thumb2/
Dthumb2-rsb2.ll9 ; CHECK: rsb.w r0, r0, #171
17 ; CHECK: rsb.w r0, r0, #1179666
25 ; CHECK: rsb.w r0, r0, #872428544
33 ; CHECK: rsb.w r0, r0, #1448498774
41 ; CHECK: rsb.w r0, r0, #66846720
Dthumb2-rsb.ll9 ; CHECK: rsb r0, r0, r1, lsl #5
17 ; CHECK: rsb r0, r0, r1, lsr #6
25 ; CHECK: rsb r0, r0, r1, asr #7
35 ; CHECK: rsb r0, r0, r0, ror #8
/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/Thumb2/
Dthumb2-rsb2.ll9 ; CHECK: rsb.w r0, r0, #171
17 ; CHECK: rsb.w r0, r0, #1179666
25 ; CHECK: rsb.w r0, r0, #872428544
33 ; CHECK: rsb.w r0, r0, #1448498774
41 ; CHECK: rsb.w r0, r0, #66846720
Dthumb2-rsb.ll9 ; CHECK: rsb r0, r0, r1, lsl #5
17 ; CHECK: rsb r0, r0, r1, lsr #6
25 ; CHECK: rsb r0, r0, r1, asr #7
35 ; CHECK: rsb r0, r0, r0, ror #8
/external/swiftshader/third_party/LLVM/test/CodeGen/Thumb/
Diabs.ll8 ;; rsb r0, r0, #0 (with opitmization, bpl + rsb is if-converted into rsbmi)
18 ; CHECK: rsb r0, r0, #0
/external/llvm/test/CodeGen/ARM/
Dthumb2-it-block.ll20 ; "rsb" inside an IT block, not "rsbs".
21 ; CHECK-NEXT: rsb{{s?}}mi
24 ; CHECK-NEXT: rsb{{s?}}mi
Dlong_shift.ll32 ; CHECK-LE-NEXT: rsb r3, r2, #32
39 ; CHECK-BE-NEXT: rsb r2, r3, #32
53 ; CHECK-LE-NEXT: rsb r3, r2, #32
60 ; CHECK-BE-NEXT: rsb r2, r3, #32
Dmul_const.ll14 ; CHECK: rsb r0, r0, r0, lsl #3
48 ; CHECK: rsb r0, r0, #0
65 ; CHECK: rsb r0, r0, #0
/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/ARM/
Dthumb2-it-block.ll20 ; "rsb" inside an IT block, not "rsbs".
21 ; CHECK-NEXT: rsb{{s?}}mi
24 ; CHECK-NEXT: rsb{{s?}}mi
Dlong_shift.ll31 ; CHECK-LE: rsb r3, r2, #32
38 ; CHECK-BE: rsb r2, r3, #32
52 ; CHECK-LE: rsb r3, r2, #32
59 ; CHECK-BE: rsb r2, r3, #32
Dmul_const.ll14 ; CHECK: rsb r0, r0, r0, lsl #3
48 ; CHECK: rsb r0, r0, #0
65 ; CHECK: rsb r0, r0, #0
Dnegate-i1.ll9 ; CHECK-NEXT: rsb r0, r0, #0
19 ; CHECK-NEXT: rsb r0, r0, #0
Dshift-i64.ll10 ; CHECK: rsb [[REVERSE_SHIFT:.*]], r2, #32
38 ; CHECK: rsb [[REVERSE_SHIFT:.*]], r2, #32
62 ; CHECK: rsb [[REVERSE_SHIFT:.*]], r2, #32
/external/llvm/test/MC/ARM/
Dbasic-arm-instructions.s1598 @ CHECK: rsb r5, r8, #0 @ encoding: [0x00,0x50,0x68,0xe2]
1939 rsb r4, r5, #0xf000
1940 rsb r4, r5, $0xf000
1941 rsb r4, r5, 0xf000
1942 rsb r7, r8, #(0xff << 16)
1943 rsb r7, r8, #-2147483638
1944 rsb r7, r8, #42, #2
1945 rsb r7, r8, #40, #2
1946 rsb r7, r8, $40, $2
1947 rsb r7, r8, 40, 2
[all …]
/external/swiftshader/third_party/llvm-7.0/llvm/test/MC/ARM/
Dbasic-arm-instructions.s1600 @ CHECK: rsb r5, r8, #0 @ encoding: [0x00,0x50,0x68,0xe2]
1941 rsb r4, r5, #0xf000
1942 rsb r4, r5, $0xf000
1943 rsb r4, r5, 0xf000
1944 rsb r7, r8, #(0xff << 16)
1945 rsb r7, r8, #-2147483638
1946 rsb r7, r8, #42, #2
1947 rsb r7, r8, #40, #2
1948 rsb r7, r8, $40, $2
1949 rsb r7, r8, 40, 2
[all …]
/external/libhevc/common/arm/
Dihevc_weighted_pred_bi_default.s148 rsb r7,r6,r3,lsl #2 @4*src_strd1 - wd
149 rsb r10,r6,r4,lsl #2 @4*src_strd2 - wd
151 @rsb r6,r6,r5,lsl #2 @4*dst_strd - wd
223 rsb r14,r9,r5,lsl #2 @4*dst_strd - wd
235 rsb r7,r6,r3,lsl #1 @2*src_strd1 - wd
236 rsb r10,r6,r4,lsl #1 @2*src_strd2 - wd
264 rsb r14,r9,r5,lsl #1 @2*dst_strd - wd
317 rsb r14,r9,r5,lsl #2 @4*dst_strd - wd
333 rsb r7,r6,r3,lsl #1 @2*src_strd1 - wd
334 rsb r10,r6,r4,lsl #1 @2*src_strd2 - wd
[all …]
/external/libmpeg2/common/arm/
Dimpeg2_format_conv.s155 rsb r6, r6, #16
208 rsb r6, r6, #8
317 rsb r6, r6, #16
370 rsb r6, r6, #8
/external/swiftshader/third_party/subzero/tests_lit/assembler/arm32/
Drsb.ll1 ; Show that we know how to translate rsb. Uses shl as example, because it
2 ; uses rsb for type i64.
116 ; ****** Here is the example of rsb *****
117 ; ASM-NEXT: rsb r3, r2, #32
/external/capstone/suite/MC/ARM/
Dbasic-arm-instructions.s.cs439 0x00,0x50,0x68,0xe2 = rsb r5, r8, #0
538 0x0f,0x4a,0x65,0xe2 = rsb r4, r5, #61440
539 0x06,0x40,0x65,0xe0 = rsb r4, r5, r6
540 0x86,0x42,0x65,0xe0 = rsb r4, r5, r6, lsl #5
542 0xa6,0x42,0x65,0xe0 = rsb r4, r5, r6, lsr #5
543 0xc6,0x42,0x65,0xe0 = rsb r4, r5, r6, asr #5
544 0xe6,0x42,0x65,0xe0 = rsb r4, r5, r6, ror #5
545 0x18,0x69,0x67,0xe0 = rsb r6, r7, r8, lsl r9
546 0x38,0x69,0x67,0xe0 = rsb r6, r7, r8, lsr r9
547 0x58,0x69,0x67,0xe0 = rsb r6, r7, r8, asr r9
[all …]
/external/swiftshader/third_party/LLVM/test/MC/ARM/
Dbasic-arm-instructions.s1318 rsb r4, r5, #0xf000
1319 rsb r4, r5, r6
1320 rsb r4, r5, r6, lsl #5
1322 rsb r4, r5, r6, lsr #5
1323 rsb r4, r5, r6, asr #5
1324 rsb r4, r5, r6, ror #5
1325 rsb r6, r7, r8, lsl r9
1326 rsb r6, r7, r8, lsr r9
1327 rsb r6, r7, r8, asr r9
1329 rsb r4, r5, r6, rrx
[all …]
/external/libavc/encoder/arm/
Dih264e_fmt_conv.s101 rsb r6, r6, #16
155 rsb r6, r6, #8
314 rsb r12, r12, #16
/external/swiftshader/third_party/LLVM/test/CodeGen/ARM/
Dlong_shift.ll26 ; CHECK-NEXT: rsb r3, r2, #32
39 ; CHECK-NEXT: rsb r3, r2, #32

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