| /external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/AMDGPU/ |
| D | mul.ll | 46 ; GCN: s_mul_i32
74 ; GCN-DAG: s_mul_i32
110 ; FUNC-LABEL: {{^}}s_mul_i32:
113 ; GCN: s_mul_i32 [[SRESULT:s[0-9]+]], [[SRC0]], [[SRC1]]
117 define amdgpu_kernel void @s_mul_i32(i32 addrspace(1)* %out, [8 x i32], i32 %a, [8 x i32], i32 %b) …
159 ; GCN: s_mul_i32
180 ; GCN-DAG: s_mul_i32
209 ; SI: s_mul_i32
211 ; SI: s_mul_i32
212 ; SI: s_mul_i32
[all …]
|
| D | codegen-prepare-addrmode-sext.ll | 9 ; SI-LLC: s_mul_i32
|
| D | s_mulk_i32.ll | 35 ; SI: s_mul_i32 {{s[0-9]+}}, {{s[0-9]+}}, 0x8001{{$}}
|
| D | mul_uint24-amdgcn.ll | 24 ; VI: s_mul_i32 [[MUL:s[0-9]+]]
56 ; VI: s_mul_i32
|
| D | llvm.amdgcn.sendmsg.ll | 124 ; TODO: This should use s_mul_i32 instead of v_mul_u32_u24 + v_readfirstlane!
|
| D | 32-bit-local-address-space.ll | 71 ; SI: s_mul_i32
|
| /external/llvm/test/CodeGen/AMDGPU/ |
| D | mul.ll | 46 ; SI: s_mul_i32
74 ; SI-DAG: s_mul_i32
110 ; FUNC-LABEL: {{^}}s_mul_i32:
113 ; SI: s_mul_i32 [[SRESULT:s[0-9]+]], [[SRC0]], [[SRC1]]
117 define void @s_mul_i32(i32 addrspace(1)* %out, i32 %a, i32 %b) nounwind {
159 ; SI: s_mul_i32
180 ; SI-DAG: s_mul_i32
|
| D | codegen-prepare-addrmode-sext.ll | 9 ; SI-LLC: s_mul_i32
|
| D | s_mulk_i32.ll | 35 ; SI: s_mul_i32 {{s[0-9]+}}, {{s[0-9]+}}, 0x8001{{$}}
|
| D | 32-bit-local-address-space.ll | 71 ; SI: s_mul_i32
|
| /external/llvm/test/MC/AMDGPU/ |
| D | trap.s | 89 s_mul_i32 ttmp8, 0x00000324, ttmp8 label
|
| D | sop2.s | 139 s_mul_i32 s2, s4, s6 label
|
| /external/swiftshader/third_party/llvm-7.0/llvm/test/MC/AMDGPU/ |
| D | trap.s | 115 s_mul_i32 ttmp8, 0x00000324, ttmp8 label
|
| D | sop2.s | 145 s_mul_i32 s2, s4, s6 label
|
| D | gfx7_asm_all.s | 19356 s_mul_i32 s5, s1, s2 label
19359 s_mul_i32 s103, s1, s2 label
19362 s_mul_i32 flat_scratch_lo, s1, s2 label
19365 s_mul_i32 flat_scratch_hi, s1, s2 label
19368 s_mul_i32 vcc_lo, s1, s2 label
19371 s_mul_i32 vcc_hi, s1, s2 label
19374 s_mul_i32 tba_lo, s1, s2 label
19377 s_mul_i32 tba_hi, s1, s2 label
19380 s_mul_i32 tma_lo, s1, s2 label
19383 s_mul_i32 tma_hi, s1, s2 label
[all …]
|
| D | gfx8_asm_all.s | 20028 s_mul_i32 s5, s1, s2 label
20031 s_mul_i32 s101, s1, s2 label
20034 s_mul_i32 flat_scratch_lo, s1, s2 label
20037 s_mul_i32 flat_scratch_hi, s1, s2 label
20040 s_mul_i32 vcc_lo, s1, s2 label
20043 s_mul_i32 vcc_hi, s1, s2 label
20046 s_mul_i32 tba_lo, s1, s2 label
20049 s_mul_i32 tba_hi, s1, s2 label
20052 s_mul_i32 tma_lo, s1, s2 label
20055 s_mul_i32 tma_hi, s1, s2 label
[all …]
|
| D | gfx9_asm_all.s | 17911 s_mul_i32 s5, s1, s2 label
17914 s_mul_i32 s101, s1, s2 label
17917 s_mul_i32 flat_scratch_lo, s1, s2 label
17920 s_mul_i32 flat_scratch_hi, s1, s2 label
17923 s_mul_i32 vcc_lo, s1, s2 label
17926 s_mul_i32 vcc_hi, s1, s2 label
17929 s_mul_i32 m0, s1, s2 label
17932 s_mul_i32 exec_lo, s1, s2 label
17935 s_mul_i32 exec_hi, s1, s2 label
17938 s_mul_i32 s5, s101, s2 label
[all …]
|
| /external/swiftshader/third_party/llvm-7.0/llvm/test/MC/Disassembler/AMDGPU/ |
| D | sop2_vi.txt | 75 # VI: s_mul_i32 s2, s4, s6 ; encoding: [0x04,0x06,0x02,0x92]
|
| D | trap_vi.txt | 67 # VI: s_mul_i32 ttmp8, 0x324, ttmp8 ; encoding: [0xff,0x78,0x78,0x92,0x24,0x03,0x00,0x00]
|
| D | trap_gfx9.txt | 58 # GFX9: s_mul_i32 ttmp8, 0x324, ttmp8 ; encoding: [0xff,0x74,0x74,0x92,0x24,0x03,0x00,0x00]
|
| /external/llvm/test/MC/Disassembler/AMDGPU/ |
| D | sop2_vi.txt | 75 # VI: s_mul_i32 s2, s4, s6 ; encoding: [0x04,0x06,0x02,0x92]
|
| D | trap_vi.txt | 67 # VI: s_mul_i32 ttmp8, 0x324, ttmp8 ; encoding: [0xff,0x78,0x78,0x92,0x24,0x03,0x00,0x00]
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AMDGPU/ |
| D | SOPInstructions.td | 457 def S_MUL_I32 : SOP2_32 <"s_mul_i32",
|
| /external/swiftshader/third_party/llvm-7.0/llvm/docs/ |
| D | AMDGPUAsmGFX7.rst | 451 s_mul_i32 dst, src0, src1
|
| /external/llvm/lib/Target/AMDGPU/ |
| D | SIInstructions.td | 301 defm S_MUL_I32 : SOP2_32 <sop2<0x26, 0x24>, "s_mul_i32",
|