1; RUN: llc -march=amdgcn -mcpu=bonaire -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s 2; RUN: llc -march=amdgcn -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s 3 4; On Southern Islands GPUs the local address space(3) uses 32-bit pointers and 5; the global address space(1) uses 64-bit pointers. These tests check to make sure 6; the correct pointer size is used for the local address space. 7 8; The e{{32|64}} suffix on the instructions refers to the encoding size and not 9; the size of the operands. The operand size is denoted in the instruction name. 10; Instructions with B32, U32, and I32 in their name take 32-bit operands, while 11; instructions with B64, U64, and I64 take 64-bit operands. 12 13; FUNC-LABEL: {{^}}local_address_load: 14; SI: v_mov_b32_e{{32|64}} [[PTR:v[0-9]]] 15; SI: ds_read_b32 v{{[0-9]+}}, [[PTR]] 16define amdgpu_kernel void @local_address_load(i32 addrspace(1)* %out, i32 addrspace(3)* %in) { 17entry: 18 %0 = load i32, i32 addrspace(3)* %in 19 store i32 %0, i32 addrspace(1)* %out 20 ret void 21} 22 23; FUNC-LABEL: {{^}}local_address_gep: 24; SI: s_add_i32 [[SPTR:s[0-9]]] 25; SI: v_mov_b32_e32 [[VPTR:v[0-9]+]], [[SPTR]] 26; SI: ds_read_b32 [[VPTR]] 27define amdgpu_kernel void @local_address_gep(i32 addrspace(1)* %out, i32 addrspace(3)* %in, i32 %offset) { 28entry: 29 %0 = getelementptr i32, i32 addrspace(3)* %in, i32 %offset 30 %1 = load i32, i32 addrspace(3)* %0 31 store i32 %1, i32 addrspace(1)* %out 32 ret void 33} 34 35; FUNC-LABEL: {{^}}local_address_gep_const_offset: 36; SI: v_mov_b32_e32 [[VPTR:v[0-9]+]], s{{[0-9]+}} 37; SI: ds_read_b32 v{{[0-9]+}}, [[VPTR]] offset:4 38define amdgpu_kernel void @local_address_gep_const_offset(i32 addrspace(1)* %out, i32 addrspace(3)* %in) { 39entry: 40 %0 = getelementptr i32, i32 addrspace(3)* %in, i32 1 41 %1 = load i32, i32 addrspace(3)* %0 42 store i32 %1, i32 addrspace(1)* %out 43 ret void 44} 45 46; Offset too large, can't fold into 16-bit immediate offset. 47; FUNC-LABEL: {{^}}local_address_gep_large_const_offset: 48; SI: s_add_i32 [[SPTR:s[0-9]]], s{{[0-9]+}}, 0x10004 49; SI: v_mov_b32_e32 [[VPTR:v[0-9]+]], [[SPTR]] 50; SI: ds_read_b32 [[VPTR]] 51define amdgpu_kernel void @local_address_gep_large_const_offset(i32 addrspace(1)* %out, i32 addrspace(3)* %in) { 52entry: 53 %0 = getelementptr i32, i32 addrspace(3)* %in, i32 16385 54 %1 = load i32, i32 addrspace(3)* %0 55 store i32 %1, i32 addrspace(1)* %out 56 ret void 57} 58 59; FUNC-LABEL: {{^}}null_32bit_lds_ptr: 60; SI: v_cmp_ne_u32 61; SI-NOT: v_cmp_ne_u32 62; SI: v_cndmask_b32 63define amdgpu_kernel void @null_32bit_lds_ptr(i32 addrspace(1)* %out, i32 addrspace(3)* %lds) nounwind { 64 %cmp = icmp ne i32 addrspace(3)* %lds, null 65 %x = select i1 %cmp, i32 123, i32 456 66 store i32 %x, i32 addrspace(1)* %out 67 ret void 68} 69 70; FUNC-LABEL: {{^}}mul_32bit_ptr: 71; SI: s_mul_i32 72; SI-NEXT: s_add_i32 73; SI: ds_read_b32 74define amdgpu_kernel void @mul_32bit_ptr(float addrspace(1)* %out, [3 x float] addrspace(3)* %lds, i32 %tid) { 75 %ptr = getelementptr [3 x float], [3 x float] addrspace(3)* %lds, i32 %tid, i32 0 76 %val = load float, float addrspace(3)* %ptr 77 store float %val, float addrspace(1)* %out 78 ret void 79} 80 81@g_lds = addrspace(3) global float undef, align 4 82 83; FUNC-LABEL: {{^}}infer_ptr_alignment_global_offset: 84; SI: v_mov_b32_e32 [[REG:v[0-9]+]], 0 85; SI: ds_read_b32 v{{[0-9]+}}, [[REG]] 86define amdgpu_kernel void @infer_ptr_alignment_global_offset(float addrspace(1)* %out, i32 %tid) { 87 %val = load float, float addrspace(3)* @g_lds 88 store float %val, float addrspace(1)* %out 89 ret void 90} 91 92 93@ptr = addrspace(3) global i32 addrspace(3)* undef 94@dst = addrspace(3) global [16383 x i32] undef 95 96; FUNC-LABEL: {{^}}global_ptr: 97; SI: ds_write_b32 98define amdgpu_kernel void @global_ptr() nounwind { 99 store i32 addrspace(3)* getelementptr ([16383 x i32], [16383 x i32] addrspace(3)* @dst, i32 0, i32 16), i32 addrspace(3)* addrspace(3)* @ptr 100 ret void 101} 102 103; FUNC-LABEL: {{^}}local_address_store: 104; SI: ds_write_b32 105define amdgpu_kernel void @local_address_store(i32 addrspace(3)* %out, i32 %val) { 106 store i32 %val, i32 addrspace(3)* %out 107 ret void 108} 109 110; FUNC-LABEL: {{^}}local_address_gep_store: 111; SI: s_add_i32 [[SADDR:s[0-9]+]], 112; SI: v_mov_b32_e32 [[ADDR:v[0-9]+]], [[SADDR]] 113; SI: ds_write_b32 [[ADDR]], v{{[0-9]+}} 114define amdgpu_kernel void @local_address_gep_store(i32 addrspace(3)* %out, i32, i32 %val, i32 %offset) { 115 %gep = getelementptr i32, i32 addrspace(3)* %out, i32 %offset 116 store i32 %val, i32 addrspace(3)* %gep, align 4 117 ret void 118} 119 120; FUNC-LABEL: {{^}}local_address_gep_const_offset_store: 121; SI: v_mov_b32_e32 [[VPTR:v[0-9]+]], s{{[0-9]+}} 122; SI: v_mov_b32_e32 [[VAL:v[0-9]+]], s{{[0-9]+}} 123; SI: ds_write_b32 [[VPTR]], [[VAL]] offset:4 124define amdgpu_kernel void @local_address_gep_const_offset_store(i32 addrspace(3)* %out, i32 %val) { 125 %gep = getelementptr i32, i32 addrspace(3)* %out, i32 1 126 store i32 %val, i32 addrspace(3)* %gep, align 4 127 ret void 128} 129 130; Offset too large, can't fold into 16-bit immediate offset. 131; FUNC-LABEL: {{^}}local_address_gep_large_const_offset_store: 132; SI: s_add_i32 [[SPTR:s[0-9]]], s{{[0-9]+}}, 0x10004 133; SI: v_mov_b32_e32 [[VPTR:v[0-9]+]], [[SPTR]] 134; SI: ds_write_b32 [[VPTR]], v{{[0-9]+$}} 135define amdgpu_kernel void @local_address_gep_large_const_offset_store(i32 addrspace(3)* %out, i32 %val) { 136 %gep = getelementptr i32, i32 addrspace(3)* %out, i32 16385 137 store i32 %val, i32 addrspace(3)* %gep, align 4 138 ret void 139} 140