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Searched refs:sde_to_rst (Results 1 – 25 of 30) sorted by relevance

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/external/u-boot/board/engicam/common/
Dspl.c246 .sde_to_rst = 0x10,
278 .sde_to_rst = 0x10,
295 .sde_to_rst = 0x10,
343 .sde_to_rst = 0x10, /* 14 cycles, 200us (JEDEC default) */
/external/u-boot/board/liebherr/mccmon6/
Dspl.c187 .sde_to_rst = 0x10,
228 .sde_to_rst = 0x10,
245 .sde_to_rst = 0x10,
/external/u-boot/board/wandboard/
Dspl.c236 .sde_to_rst = 0x10,
279 .sde_to_rst = 0x10,
298 .sde_to_rst = 0x10,
/external/u-boot/board/compulab/cm_fx6/
Dspl.c106 .sde_to_rst = 0x10,
173 .sde_to_rst = 0x10,
/external/u-boot/board/bachmann/ot1200/
Dot1200_spl.c83 .sde_to_rst = 0x10, /* 14 cycles, 200us (JEDEC default) */
/external/u-boot/board/ccv/xpress/
Dspl.c59 .sde_to_rst = 0x10, /* 14 cycles, 200us (JEDEC default) */
/external/u-boot/board/barco/platinum/
Dspl_picon.c135 .sde_to_rst = 0x10, /* 14 cycles, 200us (JEDEC default) */ in spl_dram_init()
Dspl_titanium.c138 .sde_to_rst = 0x10, /* 14 cycles, 200us (JEDEC default) */ in spl_dram_init()
/external/u-boot/board/freescale/mx6memcal/
Dspl.c230 .sde_to_rst = 0x10, /* JEDEC value for LPDDR2 - 200us */
235 .sde_to_rst = 0, /* LPDDR2 does not need this field */
/external/u-boot/arch/arm/mach-imx/mx6/
Dlitesom.c127 .sde_to_rst = 0x10, /* 14 cycles, 200us (JEDEC default) */
Dopos6ul.c192 .sde_to_rst = 0x10, /* 14 cycles, 200us (JEDEC default) */
/external/u-boot/board/bticino/mamoj/
Dspl.c125 .sde_to_rst = 0x10,
/external/u-boot/board/liebherr/display5/
Dspl.c179 .sde_to_rst = 0x10, /* 14 cycles, 200us (JEDEC default) */ in spl_dram_init()
/external/u-boot/board/udoo/
Dudoo_spl.c193 .sde_to_rst = 0x10,
/external/u-boot/board/freescale/mx6ul_14x14_evk/
Dmx6ul_14x14_evk.c765 .sde_to_rst = 0, /* LPDDR2 does not need this field */
805 .sde_to_rst = 0x10, /* 14 cycles, 200us (JEDEC default) */
/external/u-boot/board/k+p/kp_imx6q_tpc/
Dkp_imx6q_tpc_spl.c242 .sde_to_rst = 0x10, /* 14 cycles, 200us (JEDEC default) */ in spl_dram_init()
/external/u-boot/board/sks-kinkel/sksimx6/
Dsksimx6.c334 .sde_to_rst = 0x10,
/external/u-boot/board/freescale/mx6slevk/
Dmx6slevk.c411 .sde_to_rst = 0, /* LPDDR2 does not need this field */ in spl_dram_init()
/external/u-boot/board/dhelectronics/dh_imx6/
Ddh_imx6_spl.c179 .sde_to_rst = 0x10, /* 14 cycles, 200us (JEDEC default) */
/external/u-boot/board/gateworks/gw_ventana/
Dgw_ventana_spl.c447 .sde_to_rst = 0x10, /* 14 cycles, 200us (JEDEC default) */ in spl_dram_init()
/external/u-boot/board/kosagi/novena/
Dnovena_spl.c518 .sde_to_rst = 0x10, /* 14 cycles, 200us (JEDEC default) */
/external/u-boot/board/phytec/pcm058/
Dpcm058.c505 .sde_to_rst = 0x10, /* 14 cycles, 200us (JEDEC default) */ in spl_dram_init()
/external/u-boot/board/udoo/neo/
Dneo.c558 .sde_to_rst = 0x10, /* 14 cycles, 200us (JEDEC default) */ in spl_dram_init()
/external/u-boot/board/freescale/mx6sxsabresd/
Dmx6sxsabresd.c546 .sde_to_rst = 0x10, /* 14 cycles, 200us (JEDEC default) */ in spl_dram_init()
/external/u-boot/arch/arm/include/asm/arch-mx6/
Dmx6-ddr.h407 u8 sde_to_rst; /* Time from SDE enable until DDR reset# is high */ member

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