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1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3  * Copyright (C) 2014 Stefan Roese <sr@denx.de>
4  *
5  * Based on: gw_ventana_spl.c which is:
6  * Copyright (C) 2014 Gateworks Corporation
7  */
8 
9 #include <common.h>
10 #include <i2c.h>
11 #include <asm/io.h>
12 #include <asm/arch/iomux.h>
13 #include <asm/arch/mx6-ddr.h>
14 #include <asm/arch/mx6-pins.h>
15 #include <asm/arch/sys_proto.h>
16 #include <asm/mach-imx/boot_mode.h>
17 #include <asm/mach-imx/iomux-v3.h>
18 #include <asm/mach-imx/mxc_i2c.h>
19 #include <spl.h>
20 
21 #include "platinum.h"
22 
23 #undef RTT_NOM_120OHM	/* use 120ohm Rtt_nom vs 60ohm (lower power) */
24 
25 /* Configure MX6Q/DUAL mmdc DDR io registers */
26 struct mx6sdl_iomux_ddr_regs mx6sdl_ddr_ioregs = {
27 	/* SDCLK[0:1], CAS, RAS, Reset: Differential input, 40ohm */
28 	.dram_sdclk_0 = 0x00020030,
29 	.dram_sdclk_1 = 0x00020030,
30 	.dram_cas = 0x00020030,
31 	.dram_ras = 0x00020030,
32 	.dram_reset = 0x00020030,
33 	/* SDCKE[0:1]: 100k pull-up */
34 	.dram_sdcke0 = 0x00003000,
35 	.dram_sdcke1 = 0x00003000,
36 	/* SDBA2: pull-up disabled */
37 	.dram_sdba2 = 0x00000000,
38 	/* SDODT[0:1]: 100k pull-up, 40 ohm */
39 	.dram_sdodt0 = 0x00003030,
40 	.dram_sdodt1 = 0x00003030,
41 	/* SDQS[0:7]: Differential input, 40 ohm */
42 	.dram_sdqs0 = 0x00000030,
43 	.dram_sdqs1 = 0x00000030,
44 	.dram_sdqs2 = 0x00000030,
45 	.dram_sdqs3 = 0x00000030,
46 	.dram_sdqs4 = 0x00000030,
47 	.dram_sdqs5 = 0x00000030,
48 	.dram_sdqs6 = 0x00000030,
49 	.dram_sdqs7 = 0x00000030,
50 	/* DQM[0:7]: Differential input, 40 ohm */
51 	.dram_dqm0 = 0x00020030,
52 	.dram_dqm1 = 0x00020030,
53 	.dram_dqm2 = 0x00020030,
54 	.dram_dqm3 = 0x00020030,
55 	.dram_dqm4 = 0x00020030,
56 	.dram_dqm5 = 0x00020030,
57 	.dram_dqm6 = 0x00020030,
58 	.dram_dqm7 = 0x00020030,
59 };
60 
61 /* Configure MX6Q/DUAL mmdc GRP io registers */
62 struct mx6sdl_iomux_grp_regs mx6sdl_grp_ioregs = {
63 	/* DDR3 */
64 	.grp_ddr_type = 0x000c0000,
65 	.grp_ddrmode_ctl = 0x00020000,
66 	/* disable DDR pullups */
67 	.grp_ddrpke = 0x00000000,
68 	/* ADDR[00:16], SDBA[0:1]: 40 ohm */
69 	.grp_addds = 0x00000030,
70 	/* CS0/CS1/SDBA2/CKE0/CKE1/SDWE: 40 ohm */
71 	.grp_ctlds = 0x00000030,
72 	/* DATA[00:63]: Differential input, 40 ohm */
73 	.grp_ddrmode = 0x00020000,
74 	.grp_b0ds = 0x00000030,
75 	.grp_b1ds = 0x00000030,
76 	.grp_b2ds = 0x00000030,
77 	.grp_b3ds = 0x00000030,
78 	.grp_b4ds = 0x00000030,
79 	.grp_b5ds = 0x00000030,
80 	.grp_b6ds = 0x00000030,
81 	.grp_b7ds = 0x00000030,
82 };
83 
84 /* MT41K256M16HA-125 */
85 static struct mx6_ddr3_cfg mt41k256m16ha_125 = {
86 	.mem_speed = 1600,
87 	.density = 4,		/* 4Gbit */
88 	.width = 16,
89 	.banks = 8,
90 	.rowaddr = 15,
91 	.coladdr = 10,
92 	.pagesz = 2,
93 	.trcd = 1375,
94 	.trcmin = 4875,
95 	.trasmin = 3500,
96 };
97 
98 /*
99  * Values from running the Freescale DDR stress tool via USB
100  */
101 static struct mx6_mmdc_calibration mx6dq_mmdc_calib = {
102 	/* write leveling calibration determine */
103 	.p0_mpwldectrl0 = 0x0044004E,
104 	.p0_mpwldectrl1 = 0x001F0023,
105 	/* Read DQS Gating calibration */
106 	.p0_mpdgctrl0 = 0x02480248,
107 	.p0_mpdgctrl1 = 0x0210021C,
108 	/* Read Calibration: DQS delay relative to DQ read access */
109 	.p0_mprddlctl = 0x42444444,
110 	/* Write Calibration: DQ/DM delay relative to DQS write access */
111 	.p0_mpwrdlctl = 0x36322C32,
112 };
113 
spl_dram_init(int width)114 static void spl_dram_init(int width)
115 {
116 	struct mx6_ddr3_cfg *mem = &mt41k256m16ha_125;
117 	struct mx6_ddr_sysinfo sysinfo = {
118 		/* width of data bus:0=16,1=32,2=64 */
119 		.dsize = width / 32,
120 		/* config for full 4GB range so that get_mem_size() works */
121 		.cs_density = 32, /* 32Gb per CS */
122 		/* single chip select */
123 		.ncs = 1,
124 		.cs1_mirror = 1,
125 		.rtt_wr = 1 /*DDR3_RTT_60_OHM*/,	/* RTT_Wr = RZQ/4 */
126 #ifdef RTT_NOM_120OHM
127 		.rtt_nom = 2 /*DDR3_RTT_120_OHM*/,	/* RTT_Nom = RZQ/2 */
128 #else
129 		.rtt_nom = 1 /*DDR3_RTT_60_OHM*/,	/* RTT_Nom = RZQ/4 */
130 #endif
131 		.walat = 0,	/* Write additional latency */
132 		.ralat = 5,	/* Read additional latency */
133 		.mif3_mode = 3,	/* Command prediction working mode */
134 		.bi_on = 1,	/* Bank interleaving enabled */
135 		.sde_to_rst = 0x10,	/* 14 cycles, 200us (JEDEC default) */
136 		.rst_to_cke = 0x23,	/* 33 cycles, 500us (JEDEC default) */
137 		.ddr_type = DDR_TYPE_DDR3,
138 		.refsel = 1,	/* Refresh cycles at 32KHz */
139 		.refr = 7, 	/* 8 refresh commands per refresh cycle */
140 	};
141 
142 	mx6sdl_dram_iocfg(width, &mx6sdl_ddr_ioregs, &mx6sdl_grp_ioregs);
143 	mx6_dram_cfg(&sysinfo, &mx6dq_mmdc_calib, mem);
144 }
145 
146 /*
147  * Called from C runtime startup code (arch/arm/lib/crt0.S:_main)
148  * - we have a stack and a place to store GD, both in SRAM
149  * - no variable global data is available
150  */
board_init_f(ulong dummy)151 void board_init_f(ulong dummy)
152 {
153 	/* Setup AIPS and disable watchdog */
154 	arch_cpu_init();
155 
156 	ccgr_init();
157 	gpr_init();
158 
159 	/* UART iomux */
160 	board_early_init_f();
161 
162 	/* Setup GP timer */
163 	timer_init();
164 
165 	/* UART clocks enabled and gd valid - init serial console */
166 	preloader_console_init();
167 
168 	/* Init DDR with 32bit width */
169 	spl_dram_init(32);
170 
171 	/* Clear the BSS */
172 	memset(__bss_start, 0, __bss_end - __bss_start);
173 
174 	/*
175 	 * Setup enet related MUXing early to give the PHY
176 	 * some time to wake-up from reset
177 	 */
178 	platinum_setup_enet();
179 
180 	/* load/boot image from boot device */
181 	board_init_r(NULL, 0);
182 }
183