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/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AMDGPU/
DSOPInstructions.td72 bits<7> sdst;
77 let Inst{22-16} = !if(ps.has_sdst, sdst, ?);
82 opName, (outs SReg_32:$sdst), (ins SSrc_b32:$src0),
83 "$sdst, $src0", pattern
100 opName, (outs SReg_64:$sdst), (ins SSrc_b64:$src0),
101 "$sdst, $src0", pattern
106 opName, (outs SReg_32:$sdst), (ins SSrc_b64:$src0),
107 "$sdst, $src0", pattern
112 opName, (outs SReg_64:$sdst), (ins SSrc_b32:$src0),
113 "$sdst, $src0", pattern
[all …]
DSMInstructions.td61 bits<7> sdst;
112 (outs dstClass:$sdst),
114 " $sdst, $sbase, $offset$glc", []> {
122 (outs dstClass:$sdst),
124 " $sdst, $sbase, $offset$glc", []> {
158 opName, (outs SReg_64_XEXEC:$sdst), (ins),
159 " $sdst", [(set i64:$sdst, (node))]> {
207 !if(isRet, (outs dataClass:$sdst), (outs)),
211 !if(isRet, " $sdst", " $sdata") # ", $sbase, $offset" # !if(isRet, " glc", ""),
218 let Constraints = !if(isRet, "$sdst = $sdata", "");
[all …]
DVOPCInstructions.td60 let Outs64 = (outs VOPDstS64:$sdst);
117 // This class is used only with VOPC instructions. Use $sdst for out operand
128 (inst p.DstRC:$sdst),
131 (inst p.DstRC:$sdst, p.Src0RC32:$src0),
134 (inst p.DstRC:$sdst, p.Src0RC32:$src0, p.Src1RC32:$src1),
154 [(set i1:$sdst,
161 [(set i1:$sdst, (setcc P.Src0VT:$src0, P.Src1VT:$src1, cond))]);
537 let Asm64 = "$sdst, $src0_modifiers, $src1";
551 [(set i1:$sdst,
691 // Differs from VOP3e by destination name (sdst) as VOPC doesn't have vector dst
[all …]
DVOPInstructions.td247 bits<7> sdst;
251 let Inst{14-8} = sdst;
394 bits<8> sdst; // {vcc_sdst{0}, sdst{6-0}}
396 let Inst{46-40} = !if(P.EmitDst, sdst{6-0}, 0);
397 let Inst{47} = !if(P.EmitDst, sdst{7}, 0);
DSIPeepholeSDWA.cpp876 const MachineOperand *SDst = TII->getNamedOperand(MI, AMDGPU::OpName::sdst); in isConvertibleToSDWA()
886 } else if (TII->getNamedOperand(MI, AMDGPU::OpName::sdst) || in isConvertibleToSDWA()
930 } else if ((Dst = TII->getNamedOperand(MI, AMDGPU::OpName::sdst))) { in convertToSDWA()
932 AMDGPU::getNamedOperandIdx(SDWAOpcode, AMDGPU::OpName::sdst) != -1); in convertToSDWA()
935 assert(AMDGPU::getNamedOperandIdx(SDWAOpcode, AMDGPU::OpName::sdst) != -1); in convertToSDWA()
DSIInstrInfo.td1470 (outs DstRCSDWA:$sdst),
1479 string dst = !if(!eq(DstVT.Size, 1), "$sdst", "$vdst"); // use $sdst for VOPC
1493 string dst = !if(!eq(DstVT.Size, 1), "$sdst", "$vdst"); // use $sdst for VOPC
1556 "$sdst",
1558 ""); // use $sdst for VOPC
1601 "$sdst", // VOPC
DVOP3Instructions.td194 let Outs64 = (outs DstRC:$vdst, SReg_64:$sdst);
195 let Asm64 = " $vdst, $sdst, $src0, $src1, $src2";
214 let Outs64 = (outs DstRC:$vdst, SReg_64:$sdst);
215 let Asm64 = " $vdst, $sdst, $src0, $src1, $src2$clamp";
DVOP2Instructions.td252 let Asm64 = "$vdst, $sdst, $src0, $src1";
257 let Outs64 = (outs DstRC:$vdst, SReg_64:$sdst);
270 let Asm64 = "$vdst, $sdst, $src0, $src1, $src2";
275 let Outs64 = (outs DstRC:$vdst, SReg_64:$sdst);
DSIInstructions.td125 def EXIT_WWM : SPseudoInstSI <(outs SReg_64:$sdst), (ins SReg_64:$src0)> {
158 (outs SReg_64:$vdst, VOPDstS64:$sdst), (ins SSrc_b64:$src0, SSrc_b64:$src1)
162 (outs SReg_64:$vdst, VOPDstS64:$sdst), (ins SSrc_b64:$src0, SSrc_b64:$src1)
168 def GET_GROUPSTATICSIZE : PseudoInstSI <(outs SReg_32:$sdst), (ins),
169 [(set SReg_32:$sdst, (int_amdgcn_groupstaticsize))]>;
DSILoadStoreOptimizer.cpp666 const auto *Dest0 = TII->getNamedOperand(*CI.I, AMDGPU::OpName::sdst); in mergeSBufferLoadImmPair()
667 const auto *Dest1 = TII->getNamedOperand(*CI.Paired, AMDGPU::OpName::sdst); in mergeSBufferLoadImmPair()
DSIShrinkInstructions.cpp465 AMDGPU::OpName::sdst); in runOnMachineFunction()
DAMDGPU.td215 def FeatureSDWASdst : SubtargetFeature<"sdwa-sdst",
DSIInstrInfo.cpp429 FirstDst = getNamedOperand(FirstLdSt, AMDGPU::OpName::sdst); in shouldClusterMemOps()
430 SecondDst = getNamedOperand(SecondLdSt, AMDGPU::OpName::sdst); in shouldClusterMemOps()
3970 MRI.replaceRegWith(getNamedOperand(Inst, AMDGPU::OpName::sdst)->getReg(), in moveToVALU()
/external/llvm/lib/Target/AMDGPU/
DSIInstrFormats.td182 bits<7> sdst;
187 let Inst{22-16} = sdst;
192 bits<7> sdst;
198 let Inst{22-16} = sdst;
214 bits <7> sdst;
218 let Inst{22-16} = sdst;
224 bits <7> sdst = 0;
229 let Inst{22-16} = sdst;
245 bits<7> sdst;
250 let Inst{21-15} = sdst;
[all …]
DVIInstrFormats.td94 bits<7> sdst;
98 let Inst{12-6} = sdst;
147 // Differs from VOP3e by destination name (sdst) as VOPC doesn't have vector dst
149 bits<8> sdst;
151 let Inst{7-0} = sdst;
162 bits<7> sdst;
167 let Inst{14-8} = sdst;
DSIInstrInfo.td756 op, opName, (outs SReg_32:$sdst), (ins SSrc_32:$src0),
757 opName#" $sdst, $src0", pattern
761 op, opName, (outs SReg_64:$sdst), (ins SSrc_64:$src0),
762 opName#" $sdst, $src0", pattern
767 def "" : SOP1_Pseudo <opName, (outs SReg_64:$sdst), (ins), pattern>;
769 def _si : SOP1_Real_si <op, opName, (outs SReg_64:$sdst), (ins),
770 opName#" $sdst"> {
774 def _vi : SOP1_Real_vi <op, opName, (outs SReg_64:$sdst), (ins),
775 opName#" $sdst"> {
786 let sdst = 0;
[all …]
DSIInstructions.td79 (outs SReg_64:$sdst), ?, " $sdst", [(set i64:$sdst, (int_amdgcn_s_memtime))]
104 [(set i32:$sdst, (not i32:$src0))]
108 [(set i64:$sdst, (not i64:$src0))]
116 [(set i32:$sdst, (bitreverse i32:$src0))]
124 [(set i32:$sdst, (ctpop i32:$src0))]
132 [(set i32:$sdst, (cttz_zero_undef i32:$src0))]
137 [(set i32:$sdst, (AMDGPUffbh_u32 i32:$src0))]
142 [(set i32:$sdst, (int_AMDGPU_flbit_i32 i32:$src0))]
146 [(set i32:$sdst, (sext_inreg i32:$src0, i8))]
149 [(set i32:$sdst, (sext_inreg i32:$src0, i16))]
[all …]
DSILowerControlFlow.cpp548 MachineOperand *SaveOp = TII->getNamedOperand(MI, AMDGPU::OpName::sdst); in loadM0()
DSIInstrInfo.cpp311 FirstDst = getNamedOperand(FirstLdSt, AMDGPU::OpName::sdst); in shouldClusterMemOps()
312 SecondDst = getNamedOperand(SecondLdSt, AMDGPU::OpName::sdst); in shouldClusterMemOps()
/external/icu/icu4j/main/classes/localespi/src/com/ibm/icu/impl/javaspi/util/
DTimeZoneNameProviderICU.java35 String sdst = tznames.getDisplayName(canonicalID, NameType.SHORT_DAYLIGHT, date); in getDisplayName() local
37 if (lstd != null && ldst != null && sstd != null && sdst != null) { in getDisplayName()
43 dispName = daylight ? sdst : sstd; in getDisplayName()
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AMDGPU/Disassembler/
DAMDGPUDisassembler.cpp271 if (AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::sdst) != -1) in convertSDWAInst()
275 int SDst = AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::sdst); in convertSDWAInst()
279 AMDGPU::OpName::sdst); in convertSDWAInst()
/external/mesa3d/src/gallium/drivers/nouveau/nv50/
Dnv50_surface.c950 struct ureg_dst sdst = ureg_writemask(data, TGSI_WRITEMASK_Y); in nv50_blitter_make_fp() local
975 ureg_I2F(ureg, sdst, ssrc); in nv50_blitter_make_fp()
/external/vulkan-validation-layers/tests/
Dlayer_validation_tests.cpp3967 …bool sdst = !ImageFormatAndFeaturesSupported(gpu(), f_signed, VK_IMAGE_TILING_OPTIMAL, VK_FORMAT_F… in TEST_F() local
4042 …if (sdst) m_errorMonitor->SetDesiredFailureMsg(VK_DEBUG_REPORT_ERROR_BIT_EXT, "VUID-vkCmdBlitImage… in TEST_F()
4058 …if (sdst) m_errorMonitor->SetDesiredFailureMsg(VK_DEBUG_REPORT_ERROR_BIT_EXT, "VUID-vkCmdBlitImage… in TEST_F()