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Searched refs:setOpcode (Results 1 – 25 of 163) sorted by relevance

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/external/swiftshader/third_party/llvm-7.0/configs/common/lib/Target/Mips/
DMipsGenMCPseudoLowering.inc17 TmpInst.setOpcode(Mips::AND_V);
33 TmpInst.setOpcode(Mips::AND_V);
49 TmpInst.setOpcode(Mips::AND_V);
65 TmpInst.setOpcode(Mips::BEQ);
79 TmpInst.setOpcode(Mips::BGEZAL);
91 TmpInst.setOpcode(Mips::BGEZAL_MM);
103 TmpInst.setOpcode(Mips::BSEL_V);
122 TmpInst.setOpcode(Mips::BSEL_V);
141 TmpInst.setOpcode(Mips::BSEL_V);
160 TmpInst.setOpcode(Mips::BSEL_V);
[all …]
/external/swiftshader/third_party/LLVM/lib/Target/X86/
DX86MCInstLower.cpp219 OutMI.setOpcode(NewOpc); in LowerSubReg32_Op0()
224 OutMI.setOpcode(NewOpc); in LowerUnaryToTwoAddr()
246 Inst.setOpcode(Opcode); in SimplifyShortImmForm()
297 Inst.setOpcode(Opcode); in SimplifyShortMoveForm()
302 OutMI.setOpcode(MI->getOpcode()); in Lower()
400 OutMI.setOpcode(Opcode); in Lower()
408 OutMI.setOpcode(X86::RET); in Lower()
426 OutMI.setOpcode(Opcode); in Lower()
434 case X86::ADD16rr_DB: OutMI.setOpcode(X86::OR16rr); goto ReSimplify; in Lower()
435 case X86::ADD32rr_DB: OutMI.setOpcode(X86::OR32rr); goto ReSimplify; in Lower()
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/external/llvm/lib/Target/Hexagon/MCTargetDesc/
DHexagonMCDuplexInfo.cpp702 Result.setOpcode(Hexagon::V4_SA1_inc); in deriveSubInst()
708 Result.setOpcode(Hexagon::V4_SA1_dec); in deriveSubInst()
714 Result.setOpcode(Hexagon::V4_SA1_addsp); in deriveSubInst()
720 Result.setOpcode(Hexagon::V4_SA1_addi); in deriveSubInst()
727 Result.setOpcode(Hexagon::V4_SA1_addrx); in deriveSubInst()
733 Result.setOpcode(Hexagon::V4_SS2_allocframe); in deriveSubInst()
738 Result.setOpcode(Hexagon::V4_SA1_zxtb); in deriveSubInst()
743 Result.setOpcode(Hexagon::V4_SA1_and1); in deriveSubInst()
749 Result.setOpcode(Hexagon::V4_SA1_cmpeqi); in deriveSubInst()
758 Result.setOpcode(Hexagon::V4_SA1_combine1i); in deriveSubInst()
[all …]
DHexagonMCCompound.cpp220 CompoundInsn->setOpcode(compoundOpcode); in getCompoundInsn()
233 CompoundInsn->setOpcode(compoundOpcode); in getCompoundInsn()
247 CompoundInsn->setOpcode(compoundOpcode); in getCompoundInsn()
260 CompoundInsn->setOpcode(compoundOpcode); in getCompoundInsn()
273 CompoundInsn->setOpcode(compoundOpcode); in getCompoundInsn()
291 CompoundInsn->setOpcode(compoundOpcode); in getCompoundInsn()
310 CompoundInsn->setOpcode(compoundOpcode); in getCompoundInsn()
322 CompoundInsn->setOpcode(compoundOpcode); in getCompoundInsn()
333 CompoundInsn->setOpcode(compoundOpcode); in getCompoundInsn()
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Hexagon/MCTargetDesc/
DHexagonMCDuplexInfo.cpp711 Result.setOpcode(Hexagon::SA1_inc); in deriveSubInst()
717 Result.setOpcode(Hexagon::SA1_dec); in deriveSubInst()
724 Result.setOpcode(Hexagon::SA1_addsp); in deriveSubInst()
730 Result.setOpcode(Hexagon::SA1_addi); in deriveSubInst()
736 Result.setOpcode(Hexagon::SA1_addrx); in deriveSubInst()
742 Result.setOpcode(Hexagon::SS2_allocframe); in deriveSubInst()
747 Result.setOpcode(Hexagon::SA1_zxtb); in deriveSubInst()
752 Result.setOpcode(Hexagon::SA1_and1); in deriveSubInst()
758 Result.setOpcode(Hexagon::SA1_cmpeqi); in deriveSubInst()
767 Result.setOpcode(Hexagon::SA1_combine1i); in deriveSubInst()
[all …]
DHexagonMCCompound.cpp215 CompoundInsn->setOpcode(compoundOpcode); in getCompoundInsn()
228 CompoundInsn->setOpcode(compoundOpcode); in getCompoundInsn()
242 CompoundInsn->setOpcode(compoundOpcode); in getCompoundInsn()
255 CompoundInsn->setOpcode(compoundOpcode); in getCompoundInsn()
268 CompoundInsn->setOpcode(compoundOpcode); in getCompoundInsn()
286 CompoundInsn->setOpcode(compoundOpcode); in getCompoundInsn()
304 CompoundInsn->setOpcode(compoundOpcode); in getCompoundInsn()
315 CompoundInsn->setOpcode(compoundOpcode); in getCompoundInsn()
326 CompoundInsn->setOpcode(compoundOpcode); in getCompoundInsn()
/external/llvm/lib/Target/Hexagon/
DHexagonAsmPrinter.cpp265 Inst.setOpcode(Hexagon::A2_addi); in HexagonProcessInstruction()
289 TmpInst.setOpcode(Hexagon::L2_loadrdgp); in HexagonProcessInstruction()
308 TmpInst.setOpcode(Hexagon::L2_loadrigp); in HexagonProcessInstruction()
321 MappedInst.setOpcode(Hexagon::C2_or); in HexagonProcessInstruction()
334 MappedInst.setOpcode(Hexagon::M2_vrcmpys_acc_s1_h); in HexagonProcessInstruction()
336 MappedInst.setOpcode(Hexagon::M2_vrcmpys_acc_s1_l); in HexagonProcessInstruction()
345 MappedInst.setOpcode(Hexagon::M2_vrcmpys_s1_h); in HexagonProcessInstruction()
347 MappedInst.setOpcode(Hexagon::M2_vrcmpys_s1_l); in HexagonProcessInstruction()
357 MappedInst.setOpcode(Hexagon::M2_vrcmpys_s1rp_h); in HexagonProcessInstruction()
359 MappedInst.setOpcode(Hexagon::M2_vrcmpys_s1rp_l); in HexagonProcessInstruction()
[all …]
/external/llvm/lib/Target/XCore/Disassembler/
DXCoreDisassembler.cpp281 Inst.setOpcode(XCore::STW_2rus); in Decode2OpInstructionFail()
284 Inst.setOpcode(XCore::LDW_2rus); in Decode2OpInstructionFail()
287 Inst.setOpcode(XCore::ADD_3r); in Decode2OpInstructionFail()
290 Inst.setOpcode(XCore::SUB_3r); in Decode2OpInstructionFail()
293 Inst.setOpcode(XCore::SHL_3r); in Decode2OpInstructionFail()
296 Inst.setOpcode(XCore::SHR_3r); in Decode2OpInstructionFail()
299 Inst.setOpcode(XCore::EQ_3r); in Decode2OpInstructionFail()
302 Inst.setOpcode(XCore::AND_3r); in Decode2OpInstructionFail()
305 Inst.setOpcode(XCore::OR_3r); in Decode2OpInstructionFail()
308 Inst.setOpcode(XCore::LDW_3r); in Decode2OpInstructionFail()
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/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/XCore/Disassembler/
DXCoreDisassembler.cpp281 Inst.setOpcode(XCore::STW_2rus); in Decode2OpInstructionFail()
284 Inst.setOpcode(XCore::LDW_2rus); in Decode2OpInstructionFail()
287 Inst.setOpcode(XCore::ADD_3r); in Decode2OpInstructionFail()
290 Inst.setOpcode(XCore::SUB_3r); in Decode2OpInstructionFail()
293 Inst.setOpcode(XCore::SHL_3r); in Decode2OpInstructionFail()
296 Inst.setOpcode(XCore::SHR_3r); in Decode2OpInstructionFail()
299 Inst.setOpcode(XCore::EQ_3r); in Decode2OpInstructionFail()
302 Inst.setOpcode(XCore::AND_3r); in Decode2OpInstructionFail()
305 Inst.setOpcode(XCore::OR_3r); in Decode2OpInstructionFail()
308 Inst.setOpcode(XCore::LDW_3r); in Decode2OpInstructionFail()
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/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Hexagon/
DHexagonAsmPrinter.cpp257 T.setOpcode(Inst.getOpcode()); in ScaleVectorOffset()
286 Inst.setOpcode(Hexagon::A2_addi); in HexagonProcessInstruction()
300 Inst.setOpcode(Hexagon::A2_paddif); in HexagonProcessInstruction()
307 Inst.setOpcode(Hexagon::A2_paddit); in HexagonProcessInstruction()
314 Inst.setOpcode(Hexagon::A2_paddifnew); in HexagonProcessInstruction()
321 Inst.setOpcode(Hexagon::A2_padditnew); in HexagonProcessInstruction()
328 Inst.setOpcode(Hexagon::A2_andir); in HexagonProcessInstruction()
344 TmpInst.setOpcode(Hexagon::L2_loadrdgp); in HexagonProcessInstruction()
360 TmpInst.setOpcode(Hexagon::L2_loadrigp); in HexagonProcessInstruction()
373 MappedInst.setOpcode(Hexagon::C2_or); in HexagonProcessInstruction()
[all …]
/external/llvm/lib/Target/X86/
DX86MCInstLower.cpp268 Inst.setOpcode(Opcode); in SimplifyShortImmForm()
296 Inst.setOpcode(NewOpcode); in SimplifyMOVSX()
347 Inst.setOpcode(Opcode); in SimplifyShortMoveForm()
390 OutMI.setOpcode(MI->getOpcode()); in Lower()
444 OutMI.setOpcode(NewOpc); in Lower()
458 OutMI.setOpcode(NewOpc); in Lower()
473 OutMI.setOpcode(Opcode); in Lower()
481 OutMI.setOpcode(getRetOpcode(AsmPrinter.getSubtarget())); in Lower()
488 OutMI.setOpcode(getRetOpcode(AsmPrinter.getSubtarget())); in Lower()
497 OutMI.setOpcode(getRetOpcode(Subtarget)); in Lower()
[all …]
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/X86/
DX86MCInstLower.cpp297 Inst.setOpcode(Opcode); in SimplifyShortImmForm()
325 Inst.setOpcode(NewOpcode); in SimplifyMOVSX()
376 Inst.setOpcode(Opcode); in SimplifyShortMoveForm()
419 OutMI.setOpcode(MI->getOpcode()); in Lower()
473 OutMI.setOpcode(NewOpc); in Lower()
487 OutMI.setOpcode(NewOpc); in Lower()
502 OutMI.setOpcode(Opcode); in Lower()
510 OutMI.setOpcode(getRetOpcode(AsmPrinter.getSubtarget())); in Lower()
517 OutMI.setOpcode(getRetOpcode(AsmPrinter.getSubtarget())); in Lower()
526 OutMI.setOpcode(getRetOpcode(Subtarget)); in Lower()
[all …]
/external/swiftshader/third_party/llvm-7.0/configs/common/lib/Target/ARM/
DARMGenMCPseudoLowering.inc17 TmpInst.setOpcode(ARM::Bcc);
30 TmpInst.setOpcode(ARM::LDMIA_UPD);
55 TmpInst.setOpcode(ARM::MLA);
82 TmpInst.setOpcode(ARM::MOVr);
99 TmpInst.setOpcode(ARM::MUL);
123 TmpInst.setOpcode(ARM::SMLAL);
156 TmpInst.setOpcode(ARM::SMULL);
183 TmpInst.setOpcode(ARM::Bcc);
196 TmpInst.setOpcode(ARM::BX);
206 TmpInst.setOpcode(ARM::MOVr);
[all …]
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Hexagon/AsmParser/
DHexagonAsmParser.cpp164 MCB.setOpcode(Hexagon::BUNDLE); in HexagonAsmParser()
536 NewInst.setOpcode(MCI.getOpcode()); in canonicalizeImmediates()
1228 TmpInst.setOpcode(opCode); in makeCombineInst()
1316 Inst.setOpcode(Hexagon::A2_addi); in processInstruction()
1350 Inst.setOpcode(Hexagon::C2_cmpgti); in processInstruction()
1364 TmpInst.setOpcode(Hexagon::C2_cmpeq); in processInstruction()
1374 Inst.setOpcode(Hexagon::C2_cmpgtui); in processInstruction()
1390 Inst.setOpcode(Hexagon::A2_combinew); in processInstruction()
1405 Inst.setOpcode((Inst.getOpcode() == Hexagon::A2_tfrpt) in processInstruction()
1421 Inst.setOpcode((Inst.getOpcode() == Hexagon::A2_tfrptnew) in processInstruction()
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/external/swiftshader/third_party/LLVM/lib/Target/ARM/
DARMAsmPrinter.cpp983 BrInst.setOpcode(ARM::t2B); in EmitJump2Table()
1044 TmpInst.setOpcode(Opcode); in EmitPatchedInstruction()
1213 TmpInst.setOpcode(MI->getOpcode() == ARM::t2LEApcrel ? ARM::t2ADR in EmitInstruction()
1227 TmpInst.setOpcode(MI->getOpcode() == ARM::t2LEApcrelJT ? ARM::t2ADR in EmitInstruction()
1244 TmpInst.setOpcode(ARM::MOVr); in EmitInstruction()
1256 TmpInst.setOpcode(ARM::BX); in EmitInstruction()
1266 TmpInst.setOpcode(ARM::tMOVr); in EmitInstruction()
1276 TmpInst.setOpcode(ARM::tBX); in EmitInstruction()
1289 TmpInst.setOpcode(ARM::MOVr); in EmitInstruction()
1301 TmpInst.setOpcode(ARM::MOVr); in EmitInstruction()
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/external/llvm/lib/Target/Hexagon/AsmParser/
DHexagonAsmParser.cpp755 NewInst.setOpcode(MCI.getOpcode()); in canonicalizeImmediates()
1463 TmpInst.setOpcode(opCode); in makeCombineInst()
1539 Inst.setOpcode(Hexagon::A2_addi); in processInstruction()
1571 Inst.setOpcode(Hexagon::C2_cmpgti); in processInstruction()
1585 TmpInst.setOpcode(Hexagon::C2_cmpeq); in processInstruction()
1593 Inst.setOpcode(Hexagon::C2_cmpgtui); in processInstruction()
1609 Inst.setOpcode(Hexagon::A2_combinew); in processInstruction()
1624 Inst.setOpcode((Inst.getOpcode() == Hexagon::A2_tfrpt) in processInstruction()
1640 Inst.setOpcode((Inst.getOpcode() == Hexagon::A2_tfrptnew) in processInstruction()
1655 Inst.setOpcode(Hexagon::V6_vcombine); in processInstruction()
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/external/apache-commons-bcel/src/main/java/org/apache/bcel/generic/
DFCONST.java43 super.setOpcode(org.apache.bcel.Const.FCONST_0); in FCONST()
45 super.setOpcode(org.apache.bcel.Const.FCONST_1); in FCONST()
47 super.setOpcode(org.apache.bcel.Const.FCONST_2); in FCONST()
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AArch64/
DAArch64AsmPrinter.cpp517 MOVI.setOpcode(AArch64::MOVIv2d_ns); in EmitFMov0()
526 FMov.setOpcode(AArch64::FMOVWHr); in EmitFMov0()
531 FMov.setOpcode(AArch64::FMOVWSr); in EmitFMov0()
536 FMov.setOpcode(AArch64::FMOVXDr); in EmitFMov0()
572 TmpInst.setOpcode(AArch64::MOVIv16b_ns); in EmitInstruction()
595 TmpInst.setOpcode(AArch64::BR); in EmitInstruction()
604 TmpInst.setOpcode(AArch64::B); in EmitInstruction()
627 Adrp.setOpcode(AArch64::ADRP); in EmitInstruction()
633 Ldr.setOpcode(AArch64::LDRXui); in EmitInstruction()
641 Add.setOpcode(AArch64::ADDXri); in EmitInstruction()
[all …]
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Mips/Disassembler/
DMipsDisassembler.cpp679 MI.setOpcode(Mips::BOVC); in DecodeAddiGroupBranch()
682 MI.setOpcode(Mips::BEQC); in DecodeAddiGroupBranch()
685 MI.setOpcode(Mips::BEQZALC); in DecodeAddiGroupBranch()
707 MI.setOpcode(Mips::BOVC_MMR6); in DecodePOP35GroupBranchMMR6()
714 MI.setOpcode(Mips::BEQC_MMR6); in DecodePOP35GroupBranchMMR6()
721 MI.setOpcode(Mips::BEQZALC_MMR6); in DecodePOP35GroupBranchMMR6()
752 MI.setOpcode(Mips::BNVC); in DecodeDaddiGroupBranch()
755 MI.setOpcode(Mips::BNEC); in DecodeDaddiGroupBranch()
758 MI.setOpcode(Mips::BNEZALC); in DecodeDaddiGroupBranch()
780 MI.setOpcode(Mips::BNVC_MMR6); in DecodePOP37GroupBranchMMR6()
[all …]
/external/llvm/lib/Target/AArch64/
DAArch64AsmPrinter.cpp434 MOVI.setOpcode(AArch64::MOVIv2d_ns); in EmitFMov0()
443 FMov.setOpcode(AArch64::FMOVWSr); in EmitFMov0()
448 FMov.setOpcode(AArch64::FMOVXDr); in EmitFMov0()
493 TmpInst.setOpcode(AArch64::BR); in EmitInstruction()
502 TmpInst.setOpcode(AArch64::B); in EmitInstruction()
526 Adrp.setOpcode(AArch64::ADRP); in EmitInstruction()
532 Ldr.setOpcode(AArch64::LDRXui); in EmitInstruction()
540 Add.setOpcode(AArch64::ADDXri); in EmitInstruction()
550 TLSDescCall.setOpcode(AArch64::TLSDESCCALL); in EmitInstruction()
555 Blr.setOpcode(AArch64::BLR); in EmitInstruction()
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/ARM/Disassembler/
DARMDisassembler.cpp1875 Inst.setOpcode(ARM::RFEDA); in DecodeMemMultipleWritebackInstruction()
1878 Inst.setOpcode(ARM::RFEDA_UPD); in DecodeMemMultipleWritebackInstruction()
1881 Inst.setOpcode(ARM::RFEDB); in DecodeMemMultipleWritebackInstruction()
1884 Inst.setOpcode(ARM::RFEDB_UPD); in DecodeMemMultipleWritebackInstruction()
1887 Inst.setOpcode(ARM::RFEIA); in DecodeMemMultipleWritebackInstruction()
1890 Inst.setOpcode(ARM::RFEIA_UPD); in DecodeMemMultipleWritebackInstruction()
1893 Inst.setOpcode(ARM::RFEIB); in DecodeMemMultipleWritebackInstruction()
1896 Inst.setOpcode(ARM::RFEIB_UPD); in DecodeMemMultipleWritebackInstruction()
1899 Inst.setOpcode(ARM::SRSDA); in DecodeMemMultipleWritebackInstruction()
1902 Inst.setOpcode(ARM::SRSDA_UPD); in DecodeMemMultipleWritebackInstruction()
[all …]
/external/llvm/lib/Target/ARM/Disassembler/
DARMDisassembler.cpp1876 Inst.setOpcode(ARM::RFEDA); in DecodeMemMultipleWritebackInstruction()
1879 Inst.setOpcode(ARM::RFEDA_UPD); in DecodeMemMultipleWritebackInstruction()
1882 Inst.setOpcode(ARM::RFEDB); in DecodeMemMultipleWritebackInstruction()
1885 Inst.setOpcode(ARM::RFEDB_UPD); in DecodeMemMultipleWritebackInstruction()
1888 Inst.setOpcode(ARM::RFEIA); in DecodeMemMultipleWritebackInstruction()
1891 Inst.setOpcode(ARM::RFEIA_UPD); in DecodeMemMultipleWritebackInstruction()
1894 Inst.setOpcode(ARM::RFEIB); in DecodeMemMultipleWritebackInstruction()
1897 Inst.setOpcode(ARM::RFEIB_UPD); in DecodeMemMultipleWritebackInstruction()
1900 Inst.setOpcode(ARM::SRSDA); in DecodeMemMultipleWritebackInstruction()
1903 Inst.setOpcode(ARM::SRSDA_UPD); in DecodeMemMultipleWritebackInstruction()
[all …]
/external/llvm/lib/Target/Mips/Disassembler/
DMipsDisassembler.cpp608 MI.setOpcode(Mips::BOVC); in DecodeAddiGroupBranch()
611 MI.setOpcode(Mips::BEQC); in DecodeAddiGroupBranch()
614 MI.setOpcode(Mips::BEQZALC); in DecodeAddiGroupBranch()
636 MI.setOpcode(Mips::BOVC_MMR6); in DecodePOP35GroupBranchMMR6()
642 MI.setOpcode(Mips::BEQC_MMR6); in DecodePOP35GroupBranchMMR6()
648 MI.setOpcode(Mips::BEQZALC_MMR6); in DecodePOP35GroupBranchMMR6()
678 MI.setOpcode(Mips::BNVC); in DecodeDaddiGroupBranch()
681 MI.setOpcode(Mips::BNEC); in DecodeDaddiGroupBranch()
684 MI.setOpcode(Mips::BNEZALC); in DecodeDaddiGroupBranch()
706 MI.setOpcode(Mips::BNVC_MMR6); in DecodePOP37GroupBranchMMR6()
[all …]
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/PowerPC/AsmParser/
DPPCAsmParser.cpp885 TmpInst.setOpcode((Opcode == PPC::DCBTx || Opcode == PPC::DCBTT) ? in ProcessInstruction()
897 TmpInst.setOpcode(PPC::DCBT); in ProcessInstruction()
907 TmpInst.setOpcode(PPC::DCBTST); in ProcessInstruction()
924 TmpInst.setOpcode(PPC::DCBF); in ProcessInstruction()
933 TmpInst.setOpcode(PPC::LA); in ProcessInstruction()
942 TmpInst.setOpcode(PPC::ADDI); in ProcessInstruction()
951 TmpInst.setOpcode(PPC::ADDIS); in ProcessInstruction()
960 TmpInst.setOpcode(PPC::ADDIC); in ProcessInstruction()
969 TmpInst.setOpcode(PPC::ADDICo); in ProcessInstruction()
981 TmpInst.setOpcode(Opcode == PPC::EXTLWI? PPC::RLWINM : PPC::RLWINMo); in ProcessInstruction()
[all …]
/external/llvm/lib/Target/PowerPC/AsmParser/
DPPCAsmParser.cpp848 TmpInst.setOpcode((Opcode == PPC::DCBTx || Opcode == PPC::DCBTT) ? in ProcessInstruction()
860 TmpInst.setOpcode(PPC::DCBT); in ProcessInstruction()
870 TmpInst.setOpcode(PPC::DCBTST); in ProcessInstruction()
879 TmpInst.setOpcode(PPC::LA); in ProcessInstruction()
888 TmpInst.setOpcode(PPC::ADDI); in ProcessInstruction()
897 TmpInst.setOpcode(PPC::ADDIS); in ProcessInstruction()
906 TmpInst.setOpcode(PPC::ADDIC); in ProcessInstruction()
915 TmpInst.setOpcode(PPC::ADDICo); in ProcessInstruction()
927 TmpInst.setOpcode(Opcode == PPC::EXTLWI? PPC::RLWINM : PPC::RLWINMo); in ProcessInstruction()
941 TmpInst.setOpcode(Opcode == PPC::EXTRWI? PPC::RLWINM : PPC::RLWINMo); in ProcessInstruction()
[all …]

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