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Searched refs:setbits_le32 (Results 1 – 25 of 284) sorted by relevance

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/external/u-boot/drivers/video/sunxi/
Dsunxi_dw_hdmi.c68 setbits_le32(&phy->ctrl, BIT(0)); in sunxi_dw_hdmi_phy_init()
70 setbits_le32(&phy->ctrl, BIT(16)); in sunxi_dw_hdmi_phy_init()
71 setbits_le32(&phy->ctrl, BIT(1)); in sunxi_dw_hdmi_phy_init()
73 setbits_le32(&phy->ctrl, BIT(2)); in sunxi_dw_hdmi_phy_init()
75 setbits_le32(&phy->ctrl, BIT(3)); in sunxi_dw_hdmi_phy_init()
77 setbits_le32(&phy->ctrl, BIT(19)); in sunxi_dw_hdmi_phy_init()
79 setbits_le32(&phy->ctrl, BIT(18)); in sunxi_dw_hdmi_phy_init()
80 setbits_le32(&phy->ctrl, 7 << 4); in sunxi_dw_hdmi_phy_init()
91 setbits_le32(&phy->ctrl, 0xf << 8); in sunxi_dw_hdmi_phy_init()
92 setbits_le32(&phy->ctrl, BIT(7)); in sunxi_dw_hdmi_phy_init()
[all …]
Dsunxi_display.c106 setbits_le32(&ccm->ahb_reset1_cfg, 1 << AHB_RESET_OFFSET_HDMI); in sunxi_hdmi_hpd_detect()
108 setbits_le32(&ccm->ahb_gate1, 1 << AHB_GATE_OFFSET_HDMI); in sunxi_hdmi_hpd_detect()
111 setbits_le32(&ccm->hdmi_clk_cfg, CCM_HDMI_CTRL_GATE); in sunxi_hdmi_hpd_detect()
145 setbits_le32(&hdmi->ddc_fifo_ctrl, SUNXI_HDMI_DDC_FIFO_CTRL_CLEAR); in sunxi_hdmi_ddc_do_command()
156 setbits_le32(&hdmi->ddc_ctrl, SUNXI_HMDI_DDC_CTRL_START); in sunxi_hdmi_ddc_do_command()
226 setbits_le32(&ccm->hdmi_clk_cfg, CCM_HDMI_CTRL_DDC_GATE); in sunxi_hdmi_edid_get_mode()
350 setbits_le32(&ccm->ahb_gate1, 1 << AHB_GATE_OFFSET_DE_FE0); in sunxi_frontend_init()
351 setbits_le32(&ccm->dram_clk_gate, 1 << CCM_DRAM_GATE_OFFSET_DE_FE0); in sunxi_frontend_init()
354 setbits_le32(&de_fe->enable, SUNXI_DE_FE_ENABLE_EN); in sunxi_frontend_init()
365 setbits_le32(&de_fe->frame_ctrl, SUNXI_DE_FE_FRAME_CTRL_COEF_RDY); in sunxi_frontend_init()
[all …]
Dlcdc.c46 setbits_le32(&lcdc->ctrl, SUNXI_LCDC_CTRL_TCON_ENABLE); in lcdc_enable()
48 setbits_le32(&lcdc->tcon0_lvds_intf, SUNXI_LCDC_TCON0_LVDS_INTF_ENABLE); in lcdc_enable()
49 setbits_le32(&lcdc->lvds_ana0, SUNXI_LCDC_LVDS_ANA0); in lcdc_enable()
52 setbits_le32(&lcdc->lvds_ana0, SUNXI_LCDC_LVDS_ANA0_EN_MB); in lcdc_enable()
54 setbits_le32(&lcdc->lvds_ana0, SUNXI_LCDC_LVDS_ANA0_DRVC); in lcdc_enable()
56 setbits_le32(&lcdc->lvds_ana0, SUNXI_LCDC_LVDS_ANA0_DRVD(0x7)); in lcdc_enable()
58 setbits_le32(&lcdc->lvds_ana0, SUNXI_LCDC_LVDS_ANA0_DRVD(0xf)); in lcdc_enable()
60 setbits_le32(&lcdc->lvds_ana0, SUNXI_LCDC_LVDS_ANA0_UPDATE); in lcdc_enable()
62 setbits_le32(&lcdc->lvds_ana1, SUNXI_LCDC_LVDS_ANA1_INIT1); in lcdc_enable()
64 setbits_le32(&lcdc->lvds_ana1, SUNXI_LCDC_LVDS_ANA1_INIT2); in lcdc_enable()
[all …]
/external/u-boot/arch/x86/cpu/broadwell/
Dpch.c58 setbits_le32(HPET_BASE_ADDRESS + 0x10, 1 << 0); in broadwell_pch_early_init()
60 setbits_le32(RCB_REG(GCS), 1 << 5); in broadwell_pch_early_init()
98 setbits_le32(RCB_REG(0x3310), 0x0000002f); in pch_misc_init()
101 setbits_le32(RCB_REG(0x2314), 1 << 31 | 1 << 7); in pch_misc_init()
102 setbits_le32(RCB_REG(0x1114), 1 << 15 | 1 << 14); in pch_misc_init()
210 setbits_le32(RCB_REG(0x1100), 0x0000c13f); in pch_pm_init_magic()
240 setbits_le32(RCB_REG(0x0410), 0x00000003); in pch_pm_init_magic()
241 setbits_le32(RCB_REG(0x2618), 0x08000000); in pch_pm_init_magic()
242 setbits_le32(RCB_REG(0x2300), 0x00000002); in pch_pm_init_magic()
243 setbits_le32(RCB_REG(0x2600), 0x00000008); in pch_pm_init_magic()
[all …]
/external/u-boot/arch/x86/cpu/ivybridge/
Dlpc.c229 setbits_le32(RCB_REG(0x3310), (1 << 4) | (1 << 5) | (1 << 0)); in pch_power_options()
258 setbits_le32(RCB_REG(0x2238), (1 << 6) | (1 << 0)); in cpt_pm_init()
260 setbits_le32(RCB_REG(0x228c), 1 << 0); in cpt_pm_init()
261 setbits_le32(RCB_REG(0x1100), (1 << 13) | (1 << 14)); in cpt_pm_init()
262 setbits_le32(RCB_REG(0x0900), 1 << 14); in cpt_pm_init()
264 setbits_le32(RCB_REG(0x2314), (1 << 5) | (1 << 18)); in cpt_pm_init()
265 setbits_le32(RCB_REG(0x2320), (1 << 15) | (1 << 1)); in cpt_pm_init()
269 setbits_le32(RCB_REG(0x3340), 0xfffff); in cpt_pm_init()
270 setbits_le32(RCB_REG(0x3344), 1 << 1); in cpt_pm_init()
288 setbits_le32(RCB_REG(0x3a84), 1 << 24); /* SATA 2/3 disabled */ in cpt_pm_init()
[all …]
/external/u-boot/drivers/video/
Dbroadwell_igd.c82 setbits_le32(regs + 0xa248, 0x00000016); in haswell_early_init()
104 setbits_le32(regs + 0xa090, 0x00000000); in haswell_early_init()
105 setbits_le32(regs + 0xa098, 0x03e80000); in haswell_early_init()
106 setbits_le32(regs + 0xa09c, 0x00280000); in haswell_early_init()
107 setbits_le32(regs + 0xa0a8, 0x0001e848); in haswell_early_init()
108 setbits_le32(regs + 0xa0ac, 0x00000019); in haswell_early_init()
117 setbits_le32(regs + 0xa0b0, 0x00000000); in haswell_early_init()
118 setbits_le32(regs + 0xa0b4, 0x000003e8); in haswell_early_init()
119 setbits_le32(regs + 0xa0b8, 0x0000c350); in haswell_early_init()
122 setbits_le32(regs + 0xa010, 0x000f4240); in haswell_early_init()
[all …]
/external/u-boot/arch/arm/mach-omap2/omap3/
Dclock.c696 setbits_le32(&prcm_base->clksel_per, 0x000000FF); in prcm_init()
697 setbits_le32(&prcm_base->clksel_wkup, 1); in prcm_init()
710 setbits_le32(&prcm_base->iclken_usbhost, 1); in ehci_clocks_enable()
715 setbits_le32(&prcm_base->fclken_usbhost, 0x00000003); in ehci_clocks_enable()
717 setbits_le32(&prcm_base->iclken3_core, 0x00000004); in ehci_clocks_enable()
719 setbits_le32(&prcm_base->fclken3_core, 0x00000004); in ehci_clocks_enable()
730 setbits_le32(&prcm_base->clksel_per, 0x01); /* GPT2 = sys clk */ in per_clocks_enable()
731 setbits_le32(&prcm_base->iclken_per, 0x08); /* ICKen GPT2 */ in per_clocks_enable()
732 setbits_le32(&prcm_base->fclken_per, 0x08); /* FCKen GPT2 */ in per_clocks_enable()
735 setbits_le32(&prcm_base->clksel_per, 0x80); /* GPT9 = 32kHz clk */ in per_clocks_enable()
[all …]
/external/u-boot/arch/arm/mach-davinci/
Ddm365_lowlevel.c33 setbits_le32(&dv_pll0_regs->pllctl, in dm365_pll1_init()
48 setbits_le32(&dv_pll0_regs->pllctl, PLLCTL_PLLRST); in dm365_pll1_init()
97 setbits_le32(&dv_pll0_regs->pllctl, PLLCTL_PLLEN); in dm365_pll1_init()
115 setbits_le32(&dv_pll1_regs->pllctl, in dm365_pll2_init()
130 setbits_le32(&dv_pll1_regs->pllctl, PLLCTL_PLLRST); in dm365_pll2_init()
174 setbits_le32(&dv_pll1_regs->pllctl, PLLCTL_PLLEN); in dm365_pll2_init()
190 setbits_le32(&dv_sys_module_regs->vtpiocr, VPTIO_CLRZ); in dm365_ddr_setup()
197 setbits_le32(&dv_sys_module_regs->vtpiocr, VPTIO_IOPWRDN); in dm365_ddr_setup()
200 setbits_le32(&dv_sys_module_regs->vtpiocr, VPTIO_LOCK); in dm365_ddr_setup()
206 setbits_le32(&dv_sys_module_regs->vtpiocr, in dm365_ddr_setup()
[all …]
Dda850_lowlevel.c61 setbits_le32(&reg->pllctl, in da850_pll_init()
69 setbits_le32(&reg->pllctl, PLLCTL_PLLDIS); in da850_pll_init()
124 setbits_le32(&reg->pllcmd, PLLCMD_GOSTAT); in da850_pll_init()
137 setbits_le32(&reg->pllctl, PLLCTL_PLLRST); in da850_pll_init()
146 setbits_le32(&reg->pllctl, PLLCTL_PLLEN); in da850_pll_init()
174 setbits_le32(&davinci_syscfg1_regs->vtpio_ctl, VTP_CLKRZ); in da850_ddr_setup()
176 setbits_le32(&davinci_syscfg1_regs->vtpio_ctl, VTP_CLKRZ); in da850_ddr_setup()
183 setbits_le32(&davinci_syscfg1_regs->vtpio_ctl, VTP_LOCK); in da850_ddr_setup()
184 setbits_le32(&davinci_syscfg1_regs->vtpio_ctl, VTP_POWERDWN); in da850_ddr_setup()
186 setbits_le32(&davinci_syscfg1_regs->vtpio_ctl, VTP_IOPWRDWN); in da850_ddr_setup()
[all …]
/external/u-boot/drivers/usb/host/
Dehci-vf.c68 setbits_le32(pll_ctrl, ANADIG_PLL3_CTRL_ENABLE in usb_power_config()
75 setbits_le32(pll_ctrl, ANADIG_PLL7_CTRL_ENABLE in usb_power_config()
99 setbits_le32(usb_cmd, UCMD_RESET); in usb_phy_enable()
104 setbits_le32(phy_ctrl, USBPHY_CTRL_SFTRST); in usb_phy_enable()
115 setbits_le32(phy_ctrl, USBPHY_CTRL_ENUTMILEVEL2 | in usb_phy_enable()
125 setbits_le32(ctrl, UCTRL_OVER_CUR_POL); in usb_oc_config()
126 setbits_le32(ctrl, UCTRL_OVER_CUR_DIS); in usb_oc_config()
182 setbits_le32(&ehci->usbmode, CM_DEVICE); in ehci_hcd_init()
184 setbits_le32(&ehci->portsc, USB_EN); in ehci_hcd_init()
186 setbits_le32(&ehci->usbmode, CM_HOST); in ehci_hcd_init()
[all …]
Dutmi-armada100.c24 setbits_le32(&phy_regs->utmi_ctrl, INPKT_DELAY_SOF | PLL_PWR_UP); in utmi_phy_init()
26 setbits_le32(&phy_regs->utmi_ctrl, PHY_PWR_UP); in utmi_phy_init()
29 setbits_le32(&phy_regs->utmi_pll, N_DIVIDER << PLL_FBDIV | M_DIVIDER); in utmi_phy_init()
31 setbits_le32(&phy_regs->utmi_tx, PHSEL_VAL << CK60_PHSEL); in utmi_phy_init()
41 setbits_le32(&phy_regs->utmi_pll, VCOCAL_START); in utmi_phy_init()
46 setbits_le32(&phy_regs->utmi_tx, RCAL_START); in utmi_phy_init()
71 setbits_le32(&mpmu_regs->acgr, APB2_26M_EN | AP_26M); in utmi_init()
Dehci-omap.c99 setbits_le32(&reg, (OMAP_TLL_CHANNEL_CONF_CHANMODE_TRANSPARENT_UTMI in omap_usbhs_hsic_init()
221 setbits_le32(&reg, OMAP_UHH_HOSTCONFIG_ULPI_P1_BYPASS); in omap_ehci_hcd_init()
226 setbits_le32(&reg, OMAP_UHH_HOSTCONFIG_ULPI_P2_BYPASS); in omap_ehci_hcd_init()
231 setbits_le32(&reg, OMAP_UHH_HOSTCONFIG_ULPI_P3_BYPASS); in omap_ehci_hcd_init()
240 setbits_le32(&reg, OMAP_P1_MODE_HSIC); in omap_ehci_hcd_init()
243 setbits_le32(&reg, OMAP_P2_MODE_HSIC); in omap_ehci_hcd_init()
256 setbits_le32(&reg, OMAP_P1_MODE_HSIC); in omap_ehci_hcd_init()
259 setbits_le32(&reg, OMAP_P2_MODE_HSIC); in omap_ehci_hcd_init()
262 setbits_le32(&reg, OMAP_P3_MODE_HSIC); in omap_ehci_hcd_init()
Dohci-lpc32xx.c125 setbits_le32(&clk_pwr->usb_ctrl, CLK_USBCTRL_USBDVND_EN); in isp1301_configure()
137 setbits_le32(&clk_pwr->usb_ctrl, CLK_USBCTRL_CLK_EN1); in usbpll_setup()
140 setbits_le32(&clk_pwr->usb_ctrl, in usbpll_setup()
142 setbits_le32(&clk_pwr->usb_ctrl, CLK_USBCTRL_POSTDIV_2POW(0x01)); in usbpll_setup()
143 setbits_le32(&clk_pwr->usb_ctrl, CLK_USBCTRL_PLL_PWRUP); in usbpll_setup()
151 setbits_le32(&clk_pwr->usb_ctrl, CLK_USBCTRL_CLK_EN2); in usbpll_setup()
175 setbits_le32(&clk_pwr->usb_ctrl, in usb_cpu_init()
194 setbits_le32(&clk_pwr->usb_ctrl, CLK_USBCTRL_USBHSTND_EN); in usb_cpu_init()
206 setbits_le32(&otg->otg_sts_ctrl, OTG_HOST_EN); in usb_cpu_init()
Dehci-exynos.c98 setbits_le32(&usb->usbphyctrl0, in exynos5_setup_usb_phy()
123 setbits_le32(&usb->hsicphyctrl1, hsic_ctrl); in exynos5_setup_usb_phy()
124 setbits_le32(&usb->hsicphyctrl2, hsic_ctrl); in exynos5_setup_usb_phy()
137 setbits_le32(&usb->ehcictrl, in exynos5_setup_usb_phy()
152 setbits_le32(&usb->usbphyrstcon, (RSTCON_HOSTPHY_SWRST | RSTCON_SWRST)); in exynos4412_setup_usb_phy()
176 setbits_le32(&usb->usbphyctrl0, in exynos5_reset_usb_phy()
189 setbits_le32(&usb->hsicphyctrl1, hsic_ctrl); in exynos5_reset_usb_phy()
190 setbits_le32(&usb->hsicphyctrl2, hsic_ctrl); in exynos5_reset_usb_phy()
195 setbits_le32(&usb->usbphyctrl, (PHYPWR_NORMAL_MASK_HSIC0 | in exynos4412_reset_usb_phy()
Dehci-mx6.c148 setbits_le32(usb_cmd, UCMD_RESET); in usb_phy_enable()
154 setbits_le32(phy_ctrl, USBPHY_CTRL_SFTRST); in usb_phy_enable()
164 setbits_le32(phy_ctrl, USBPHY_CTRL_ENUTMILEVEL2 | in usb_phy_enable()
225 setbits_le32(ctrl, UCTRL_PWR_POL); in usb_power_config()
263 setbits_le32(ctrl, UCTRL_OVER_CUR_POL); in usb_oc_config()
266 setbits_le32(ctrl, UCTRL_OVER_CUR_DIS); in usb_oc_config()
374 setbits_le32(&ehci->usbmode, CM_HOST); in ehci_hcd_init()
376 setbits_le32(&ehci->portsc, USB_EN); in ehci_hcd_init()
420 setbits_le32(&ehci->usbmode, CM_HOST); in mx6_init_after_reset()
422 setbits_le32(&ehci->portsc, USB_EN); in mx6_init_after_reset()
[all …]
/external/u-boot/arch/arm/mach-socfpga/
Dreset_manager_arria10.c131 setbits_le32(&reset_manager_base->per1modrst, in socfpga_watchdog_disable()
183 setbits_le32(&reset_manager_base->per0modrst, eccmask); in socfpga_emac_manage_reset()
184 setbits_le32(&reset_manager_base->per0modrst, emacmask); in socfpga_emac_manage_reset()
218 setbits_le32(&sysmgr_regs->noc_idlereq_clr, mask_noc); in socfpga_reset_deassert_bridges_handoff()
243 setbits_le32(&reset_manager_base->per0modrst, mask0 & ECC_MASK); in socfpga_reset_assert_fpga_connected_peripherals()
244 setbits_le32(&reset_manager_base->per1modrst, mask1); in socfpga_reset_assert_fpga_connected_peripherals()
245 setbits_le32(&reset_manager_base->per0modrst, mask0); in socfpga_reset_assert_fpga_connected_peripherals()
285 setbits_le32(reg, 1 << RSTMGR_RESET(reset)); in socfpga_per_reset()
313 setbits_le32(&reset_manager_base->per0modrst, ~mask_ecc_ocp); in socfpga_per_reset_all()
316 setbits_le32(&reset_manager_base->per0modrst, mask_ecc_ocp); in socfpga_per_reset_all()
[all …]
Dfreeze_controller.c129 setbits_le32(ioctrl_reg_offset, reg_cfg_mask); in sys_mgr_frzctrl_thaw_req()
138 setbits_le32(ioctrl_reg_offset, reg_cfg_mask); in sys_mgr_frzctrl_thaw_req()
144 setbits_le32(ioctrl_reg_offset, in sys_mgr_frzctrl_thaw_req()
160 setbits_le32(&freeze_controller_base->hioctrl, in sys_mgr_frzctrl_thaw_req()
190 setbits_le32(&freeze_controller_base->hioctrl, reg_cfg_mask); in sys_mgr_frzctrl_thaw_req()
203 setbits_le32(&freeze_controller_base->hioctrl, in sys_mgr_frzctrl_thaw_req()
/external/u-boot/arch/arm/mach-exynos/
Dpower.c46 setbits_le32(&power->usbhost_phy_control, in exynos5_set_usbhost_phy_ctrl()
62 setbits_le32(&power->usbhost_phy_control, in exynos4412_set_usbhost_phy_ctrl()
64 setbits_le32(&power->hsic1_phy_control, in exynos4412_set_usbhost_phy_ctrl()
66 setbits_le32(&power->hsic2_phy_control, in exynos4412_set_usbhost_phy_ctrl()
95 setbits_le32(&power->usbdrd_phy_control, in exynos5_set_usbdrd_phy_ctrl()
111 setbits_le32(&power->usbdev_phy_control, in exynos5420_set_usbdev_phy_ctrl()
113 setbits_le32(&power->usbdev1_phy_control, in exynos5420_set_usbdev_phy_ctrl()
161 setbits_le32(&power->ps_hold_control, in exynos5_set_ps_hold_ctrl()
202 setbits_le32(&power->ps_hold_control, POWER_ENABLE_HW_TRIP); in set_hw_thermal_trip()
/external/u-boot/arch/arm/cpu/arm926ejs/mxs/
Dspl_power_init.c63 setbits_le32(&clkctrl_regs->hw_clkctrl_pll0ctrl0, in mxs_power_clock2pll()
71 setbits_le32(&clkctrl_regs->hw_clkctrl_clkseq, in mxs_power_clock2pll()
104 setbits_le32(&rtc_regs->hw_rtc_persistent0, in mxs_power_set_auto_restart()
265 setbits_le32(&power_regs->hw_power_misc, in mxs_power_switch_dcdc_clocksource()
303 setbits_le32(&power_regs->hw_power_battmonitor, in mxs_src_power_init()
316 setbits_le32(&power_regs->hw_power_5vctrl, POWER_5VCTRL_DCDC_XFER); in mxs_src_power_init()
404 setbits_le32(&power_regs->hw_power_5vctrl, in mxs_enable_4p2_dcdc_input()
410 setbits_le32(&power_regs->hw_power_5vctrl, in mxs_enable_4p2_dcdc_input()
413 setbits_le32(&power_regs->hw_power_dcdc4p2, in mxs_enable_4p2_dcdc_input()
452 setbits_le32(&power_regs->hw_power_ctrl, in mxs_enable_4p2_dcdc_input()
[all …]
/external/u-boot/drivers/fpga/
Dsocfpga_arria10.c47 setbits_le32(&fpga_manager_base->imgcfg_ctrl_02, in fpgamgr_set_cfgwdth()
133 setbits_le32(&fpga_manager_base->imgcfg_ctrl_02, in fpgamgr_set_cd_ratio()
232 setbits_le32(&fpga_manager_base->imgcfg_ctrl_00, in fpgamgr_reset()
283 setbits_le32(&fpga_manager_base->imgcfg_ctrl_01, in fpgamgr_program_init()
293 setbits_le32(&fpga_manager_base->imgcfg_ctrl_00, in fpgamgr_program_init()
316 setbits_le32(&fpga_manager_base->imgcfg_ctrl_00, in fpgamgr_program_init()
341 setbits_le32(&fpga_manager_base->imgcfg_ctrl_02, in fpgamgr_program_init()
401 setbits_le32(&fpga_manager_base->imgcfg_ctrl_01, in fpgamgr_program_poll_usermode()
403 setbits_le32(&fpga_manager_base->imgcfg_ctrl_00, in fpgamgr_program_poll_usermode()
407 setbits_le32(&fpga_manager_base->imgcfg_ctrl_01, in fpgamgr_program_poll_usermode()
/external/u-boot/arch/arm/mach-sunxi/
Ddram_sun6i.c45 setbits_le32(&ccm->ahb_reset0_cfg, 1 << AHB_RESET_OFFSET_MCTL); in mctl_sys_init()
48 setbits_le32(&ccm->ahb_gate0, 1 << AHB_GATE_OFFSET_MCTL); in mctl_sys_init()
159 setbits_le32(&mctl_phy->pir, MCTL_PIR_CLEAR_STATUS); in mctl_channel_init()
184 setbits_le32(&mctl_phy->dx2dllcr, MCTL_DLLCR_DISABLE); in mctl_channel_init()
185 setbits_le32(&mctl_phy->dx3dllcr, MCTL_DLLCR_DISABLE); in mctl_channel_init()
190 setbits_le32(&mctl_phy->pir, MCTL_PIR_CLEAR_STATUS); in mctl_channel_init()
239 setbits_le32(&mctl_ctl->dfiodtcfg, 1 << 3); in mctl_channel_init()
244 setbits_le32(&mctl_ctl->ppcfg, 1); in mctl_channel_init()
277 setbits_le32(&mctl_com->dbgcr, (1 << 6)); in mctl_com_init()
281 setbits_le32(&mctl_phy1->aciocr, MCTL_ACIOCR_DISABLE); in mctl_com_init()
[all …]
/external/u-boot/board/sunxi/
Dgmac.c17 setbits_le32(&ccm->ahb_reset0_cfg, 0x1 << AHB_RESET_OFFSET_GMAC);
18 setbits_le32(&ccm->ahb_gate0, 0x1 << AHB_GATE_OFFSET_GMAC);
20 setbits_le32(&ccm->ahb_gate1, 0x1 << AHB_GATE_OFFSET_GMAC);
25 setbits_le32(&ccm->gmac_clk_cfg, CCM_GMAC_CTRL_TX_CLK_SRC_INT_RGMII |
27 setbits_le32(&ccm->gmac_clk_cfg,
30 setbits_le32(&ccm->gmac_clk_cfg, CCM_GMAC_CTRL_TX_CLK_SRC_MII |
/external/u-boot/arch/arm/mach-omap2/omap5/
Dhw_data.c437 setbits_le32((*prcm)->cm_l4per_gpio4_clkctrl, in enable_basic_clocks()
441 setbits_le32((*prcm)->cm_l3init_hsmmc1_clkctrl, in enable_basic_clocks()
443 setbits_le32((*prcm)->cm_l3init_hsmmc2_clkctrl, in enable_basic_clocks()
453 setbits_le32((*prcm)->cm_wkup_gptimer1_clkctrl, in enable_basic_clocks()
462 setbits_le32((*prcm)->cm_l4per_qspi_clkctrl, (1<<24)); in enable_basic_clocks()
467 setbits_le32((*prcm)->cm_l3init_sata_clkctrl, in enable_basic_clocks()
472 setbits_le32((*prcm)->cm_wkupaon_scrm_clkctrl, in enable_basic_clocks()
474 setbits_le32((*prcm)->cm_wkupaon_scrm_clkctrl, in enable_basic_clocks()
562 setbits_le32((*prcm)->cm_l3init_usb_otg_ss1_clkctrl, in enable_usb_clocks()
566 setbits_le32((*prcm)->cm_coreaon_usb_phy1_core_clkctrl, in enable_usb_clocks()
[all …]
/external/u-boot/arch/arm/mach-omap2/
Dabb.c54 setbits_le32(setup, in abb_setup_timings()
106 setbits_le32(txdone, txdone_mask); in abb_setup()
109 setbits_le32(setup, abb_type_mask | OMAP_ABB_SETUP_SR2EN_MASK); in abb_setup()
112 setbits_le32(control, opp_sel_mask | OMAP_ABB_CONTROL_OPP_CHANGE_MASK); in abb_setup()
119 setbits_le32(txdone, txdone_mask); in abb_setup()
/external/u-boot/drivers/ram/stm32mp1/
Dstm32mp1_ddr.c292 setbits_le32(&ctl->swctl, DDRCTRL_SWCTL_SW_DONE); in wait_sw_done_ack()
339 setbits_le32(&ctl->rfshctl3, DDRCTRL_RFSHCTL3_DIS_AUTO_REFRESH); in stm32mp1_refresh_disable()
352 setbits_le32(&ctl->pwrctl, DDRCTRL_PWRCTL_POWERDOWN_EN); in stm32mp1_refresh_restore()
353 setbits_le32(&ctl->dfimisc, DDRCTRL_DFIMISC_DFI_INIT_COMPLETE_EN); in stm32mp1_refresh_restore()
383 setbits_le32(priv->rcc + RCC_DDRITFCR, RCC_DDRITFCR_DDRCAPBRST); in stm32mp1_ddr_init()
384 setbits_le32(priv->rcc + RCC_DDRITFCR, RCC_DDRITFCR_DDRCAXIRST); in stm32mp1_ddr_init()
385 setbits_le32(priv->rcc + RCC_DDRITFCR, RCC_DDRITFCR_DDRCORERST); in stm32mp1_ddr_init()
386 setbits_le32(priv->rcc + RCC_DDRITFCR, RCC_DDRITFCR_DPHYAPBRST); in stm32mp1_ddr_init()
387 setbits_le32(priv->rcc + RCC_DDRITFCR, RCC_DDRITFCR_DPHYRST); in stm32mp1_ddr_init()
388 setbits_le32(priv->rcc + RCC_DDRITFCR, RCC_DDRITFCR_DPHYCTLRST); in stm32mp1_ddr_init()
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