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Searched refs:shifter (Results 1 – 25 of 41) sorted by relevance

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/external/swiftshader/third_party/LLVM/test/CodeGen/MBlaze/
Dshift.ll1 ; Ensure that shifts are lowered to loops when the barrel shifter unit is
3 ; barrel shifter unit is available in the hardware.
/external/swiftshader/third_party/subzero/src/
DIceAssemblerX86Base.h662 void rol(Type Ty, GPRRegister operand, GPRRegister shifter);
663 void rol(Type Ty, const Address &operand, GPRRegister shifter);
666 void shl(Type Ty, GPRRegister operand, GPRRegister shifter);
667 void shl(Type Ty, const Address &operand, GPRRegister shifter);
670 void shr(Type Ty, GPRRegister operand, GPRRegister shifter);
671 void shr(Type Ty, const Address &operand, GPRRegister shifter);
674 void sar(Type Ty, GPRRegister operand, GPRRegister shifter);
675 void sar(Type Ty, const Address &address, GPRRegister shifter);
773 GPRRegister shifter);
DIceAssemblerX86BaseImpl.h3234 GPRRegister shifter) { in rol() argument
3235 emitGenericShift(0, Ty, Operand(operand), shifter); in rol()
3240 GPRRegister shifter) { in rol() argument
3241 emitGenericShift(0, Ty, operand, shifter); in rol()
3252 GPRRegister shifter) { in shl() argument
3253 emitGenericShift(4, Ty, Operand(operand), shifter); in shl()
3258 GPRRegister shifter) { in shl() argument
3259 emitGenericShift(4, Ty, operand, shifter); in shl()
3270 GPRRegister shifter) { in shr() argument
3271 emitGenericShift(5, Ty, Operand(operand), shifter); in shr()
[all …]
/external/mesa3d/src/gallium/drivers/radeon/
Dradeon_vcn_enc_1_2.c111 enc->shifter |= value_to_pack << (32 - enc->bits_in_shifter - bits_to_pack); in radeon_enc_code_fixed_bits()
116 unsigned char output_byte = (unsigned char)(enc->shifter >> 24); in radeon_enc_code_fixed_bits()
117 enc->shifter <<= 8; in radeon_enc_code_fixed_bits()
129 enc->shifter = 0; in radeon_enc_reset()
147 unsigned char output_byte = (unsigned char)(enc->shifter >> 24); in radeon_enc_flush_headers()
151 enc->shifter = 0; in radeon_enc_flush_headers()
Dradeon_vcn_enc.h400 unsigned shifter; member
/external/swiftshader/third_party/LLVM/lib/Target/MBlaze/
DMBlaze.td35 "Implements barrel shifter">;
/external/u-boot/doc/device-tree-bindings/exynos/
Ddwmmc.txt36 . The above 3 values are used by the clock phase shifter.
/external/capstone/arch/AArch64/
DAArch64InstPrinter.c770 arm64_shifter shifter = ARM64_SFT_INVALID; in printShifter() local
774 shifter = ARM64_SFT_LSL; in printShifter()
777 shifter = ARM64_SFT_LSR; in printShifter()
780 shifter = ARM64_SFT_ASR; in printShifter()
783 shifter = ARM64_SFT_ROR; in printShifter()
786 shifter = ARM64_SFT_MSL; in printShifter()
790 …>flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count - 1].shift.type = shifter; in printShifter()
/external/u-boot/arch/arm/dts/
Dzynqmp-zc1751-xm015-dc1.dts154 /* SD1 with level shifter */
Dzynqmp-zcu104-revA.dts217 /* SD1 with level shifter */
Dzynqmp-zcu104-revC.dts223 /* SD1 with level shifter */
Domap3-evm-processor-common.dtsi187 * for bus switch SN74CB3Q3384A, level-shifter SN74AVC16T245DGGR, and 1.8V.
Dzynqmp-zcu100-revC.dts249 /* SD0 only supports 3.3V, no level shifter */
Dzynqmp-zcu111-revA.dts497 /* SD1 with level shifter */
Dzynqmp-zcu102-revA.dts582 /* SD1 with level shifter */
Dzynqmp-zcu106-revA.dts560 /* SD1 with level shifter */
/external/swiftshader/third_party/subzero/tests_lit/llvm2ice_tests/
Dreturn_immediates.ll22 ; ARM has a shifter that allows encoding 8-bits rotated right by even amounts.
/external/swiftshader/third_party/LLVM/test/MC/ARM/
Dbasic-thumb-instructions.s11 @ For complex constructs like shifter operands, check more thoroughly for them
/external/llvm/test/MC/ARM/
Dbasic-thumb-instructions.s12 @ For complex constructs like shifter operands, check more thoroughly for them
/external/swiftshader/third_party/llvm-7.0/llvm/test/MC/ARM/
Dbasic-thumb-instructions.s12 @ For complex constructs like shifter operands, check more thoroughly for them
/external/llvm/lib/Target/ARM/
DARM.td209 "Avoid movs instructions with shifter operand">;
/external/llvm/lib/Target/AArch64/
DAArch64InstrFormats.td139 // The "MSL" shifter on the vector MOVI instruction.
572 // An arithmetic shifter operand:
594 // An arithmetic shifter operand:
616 // A logical vector shifter operand:
625 // A logical vector half-word shifter operand:
634 // A vector move shifter operand:
652 // An ADD/SUB immediate shifter operand:
1561 class BaseMoveImmediate<bits<2> opc, RegisterClass regtype, Operand shifter,
1563 : I<(outs regtype:$Rd), (ins movimm32_imm:$imm, shifter:$shift),
1589 class BaseInsertImmediate<bits<2> opc, RegisterClass regtype, Operand shifter,
[all …]
DAArch64SchedCyclone.td42 // 2 shifter pipes: I[2..3]
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/ARM/
DARM.td277 "shifter operand">;
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AArch64/
DAArch64InstrFormats.td157 // The "MSL" shifter on the vector MOVI instruction.
778 // An arithmetic shifter operand:
800 // An arithmetic shifter operand:
822 // A logical vector shifter operand:
831 // A logical vector half-word shifter operand:
840 // A vector move shifter operand:
860 // An ADD/SUB immediate shifter operand:
1919 class BaseMoveImmediate<bits<2> opc, RegisterClass regtype, Operand shifter,
1921 : I<(outs regtype:$Rd), (ins movimm32_imm:$imm, shifter:$shift),
1947 class BaseInsertImmediate<bits<2> opc, RegisterClass regtype, Operand shifter,
[all …]

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