1/* 2 * Common support for omap3 EVM 35xx/37xx processor modules 3 */ 4 5/ { 6 memory@80000000 { 7 device_type = "memory"; 8 reg = <0x80000000 0x10000000>; /* 256 MB */ 9 }; 10 11 wl12xx_vmmc: wl12xx_vmmc { 12 pinctrl-names = "default"; 13 pinctrl-0 = <&wl12xx_gpio>; 14 }; 15}; 16 17&dss { 18 vdds_dsi-supply = <&vpll2>; 19 vdda_video-supply = <&lcd_3v3>; 20 pinctrl-names = "default"; 21 pinctrl-0 = < 22 &dss_dpi_pins1 23 &dss_dpi_pins2 24 >; 25}; 26 27&hsusb2_phy { 28 pinctrl-names = "default"; 29 pinctrl-0 = <&ehci_phy_pins>; 30}; 31 32&omap3_pmx_core { 33 pinctrl-names = "default"; 34 pinctrl-0 = <&on_board_gpio_61 &hsusb2_pins>; 35 36 dss_dpi_pins1: pinmux_dss_dpi_pins2 { 37 pinctrl-single,pins = < 38 OMAP3_CORE1_IOPAD(0x20d4, PIN_OUTPUT | MUX_MODE0) /* dss_pclk.dss_pclk */ 39 OMAP3_CORE1_IOPAD(0x20d6, PIN_OUTPUT | MUX_MODE0) /* dss_hsync.dss_hsync */ 40 OMAP3_CORE1_IOPAD(0x20d8, PIN_OUTPUT | MUX_MODE0) /* dss_vsync.dss_vsync */ 41 OMAP3_CORE1_IOPAD(0x20da, PIN_OUTPUT | MUX_MODE0) /* dss_acbias.dss_acbias */ 42 43 OMAP3_CORE1_IOPAD(0x20e8, PIN_OUTPUT | MUX_MODE0) /* dss_data6.dss_data6 */ 44 OMAP3_CORE1_IOPAD(0x20ea, PIN_OUTPUT | MUX_MODE0) /* dss_data7.dss_data7 */ 45 OMAP3_CORE1_IOPAD(0x20ec, PIN_OUTPUT | MUX_MODE0) /* dss_data8.dss_data8 */ 46 OMAP3_CORE1_IOPAD(0x20ee, PIN_OUTPUT | MUX_MODE0) /* dss_data9.dss_data9 */ 47 OMAP3_CORE1_IOPAD(0x20f0, PIN_OUTPUT | MUX_MODE0) /* dss_data10.dss_data10 */ 48 OMAP3_CORE1_IOPAD(0x20f2, PIN_OUTPUT | MUX_MODE0) /* dss_data11.dss_data11 */ 49 OMAP3_CORE1_IOPAD(0x20f4, PIN_OUTPUT | MUX_MODE0) /* dss_data12.dss_data12 */ 50 OMAP3_CORE1_IOPAD(0x20f6, PIN_OUTPUT | MUX_MODE0) /* dss_data13.dss_data13 */ 51 OMAP3_CORE1_IOPAD(0x20f8, PIN_OUTPUT | MUX_MODE0) /* dss_data14.dss_data14 */ 52 OMAP3_CORE1_IOPAD(0x20fa, PIN_OUTPUT | MUX_MODE0) /* dss_data15.dss_data15 */ 53 OMAP3_CORE1_IOPAD(0x20fc, PIN_OUTPUT | MUX_MODE0) /* dss_data16.dss_data16 */ 54 OMAP3_CORE1_IOPAD(0x20fe, PIN_OUTPUT | MUX_MODE0) /* dss_data17.dss_data17 */ 55 56 OMAP3_CORE1_IOPAD(0x2100, PIN_OUTPUT | MUX_MODE3) /* dss_data18.dss_data0 */ 57 OMAP3_CORE1_IOPAD(0x2102, PIN_OUTPUT | MUX_MODE3) /* dss_data19.dss_data1 */ 58 OMAP3_CORE1_IOPAD(0x2104, PIN_OUTPUT | MUX_MODE3) /* dss_data20.dss_data2 */ 59 OMAP3_CORE1_IOPAD(0x2106, PIN_OUTPUT | MUX_MODE3) /* dss_data21.dss_data3 */ 60 OMAP3_CORE1_IOPAD(0x2108, PIN_OUTPUT | MUX_MODE3) /* dss_data22.dss_data4 */ 61 OMAP3_CORE1_IOPAD(0x210a, PIN_OUTPUT | MUX_MODE3) /* dss_data23.dss_data5 */ 62 >; 63 }; 64 65 mmc1_pins: pinmux_mmc1_pins { 66 pinctrl-single,pins = < 67 OMAP3_CORE1_IOPAD(0x2144, PIN_OUTPUT_PULLUP | MUX_MODE0) /* sdmmc1_clk.sdmmc1_clk */ 68 OMAP3_CORE1_IOPAD(0x2146, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_cmd.sdmmc1_cmd */ 69 OMAP3_CORE1_IOPAD(0x2148, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat0.sdmmc1_dat0 */ 70 OMAP3_CORE1_IOPAD(0x214a, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat1.sdmmc1_dat1 */ 71 OMAP3_CORE1_IOPAD(0x214c, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat2.sdmmc1_dat2 */ 72 OMAP3_CORE1_IOPAD(0x214e, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat3.sdmmc1_dat3 */ 73 OMAP3_CORE1_IOPAD(0x2150, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat4.sdmmc1_dat4 */ 74 OMAP3_CORE1_IOPAD(0x2152, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat5.sdmmc1_dat5 */ 75 OMAP3_CORE1_IOPAD(0x2154, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat6.sdmmc1_dat6 */ 76 OMAP3_CORE1_IOPAD(0x2156, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat7.sdmmc1_dat7 */ 77 >; 78 }; 79 80 /* NOTE: Clocked externally, needs INPUT also for sdmmc2_clk.sdmmc2_clk */ 81 mmc2_pins: pinmux_mmc2_pins { 82 pinctrl-single,pins = < 83 OMAP3_CORE1_IOPAD(0x2158, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_clk.sdmmc2_clk */ 84 OMAP3_CORE1_IOPAD(0x215a, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_cmd.sdmmc2_cmd */ 85 OMAP3_CORE1_IOPAD(0x215c, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat0.sdmmc2_dat0 */ 86 OMAP3_CORE1_IOPAD(0x215e, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat1.sdmmc2_dat1 */ 87 OMAP3_CORE1_IOPAD(0x2160, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat2.sdmmc2_dat2 */ 88 OMAP3_CORE1_IOPAD(0x2162, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat3.sdmmc2_dat3 */ 89 >; 90 }; 91 92 uart3_pins: pinmux_uart3_pins { 93 pinctrl-single,pins = < 94 OMAP3_CORE1_IOPAD(0x219e, WAKEUP_EN | PIN_INPUT | MUX_MODE0) /* uart3_rx_irrx.uart3_rx_irrx */ 95 OMAP3_CORE1_IOPAD(0x21a0, PIN_OUTPUT | MUX_MODE0) /* uart3_tx_irtx.uart3_tx_irtx */ 96 >; 97 }; 98 99 /* Devices are routed with gpmc_nbe1.gpio_61 to on-board devices */ 100 on_board_gpio_61: pinmux_ehci_port_select_pins { 101 pinctrl-single,pins = < 102 OMAP3_CORE1_IOPAD(0x20c8, PIN_OUTPUT | MUX_MODE4) 103 >; 104 }; 105 106 /* Used by OHCI and EHCI. OHCI won't work without external phy */ 107 hsusb2_pins: pinmux_hsusb2_pins { 108 pinctrl-single,pins = < 109 110 /* mcspi1_cs3.hsusb2_data2 */ 111 OMAP3_CORE1_IOPAD(0x21d4, PIN_INPUT_PULLDOWN | MUX_MODE3) 112 113 /* mcspi2_clk.hsusb2_data7 */ 114 OMAP3_CORE1_IOPAD(0x21d6, PIN_INPUT_PULLDOWN | MUX_MODE3) 115 116 /* mcspi2_simo.hsusb2_data4 */ 117 OMAP3_CORE1_IOPAD(0x21d8, PIN_INPUT_PULLDOWN | MUX_MODE3) 118 119 /* mcspi2_somi.hsusb2_data5 */ 120 OMAP3_CORE1_IOPAD(0x21da, PIN_INPUT_PULLDOWN | MUX_MODE3) 121 122 /* mcspi2_cs0.hsusb2_data6 */ 123 OMAP3_CORE1_IOPAD(0x21dc, PIN_INPUT_PULLDOWN | MUX_MODE3) 124 125 /* mcspi2_cs1.hsusb2_data3 */ 126 OMAP3_CORE1_IOPAD(0x21de, PIN_INPUT_PULLDOWN | MUX_MODE3) 127 >; 128 }; 129 130 wl12xx_gpio: pinmux_wl12xx_gpio { 131 pinctrl-single,pins = < 132 OMAP3_CORE1_IOPAD(0x2180, PIN_OUTPUT | MUX_MODE4) /* uart1_cts.gpio_150 */ 133 OMAP3_CORE1_IOPAD(0x217e, PIN_INPUT | MUX_MODE4) /* uart1_rts.gpio_149 */ 134 >; 135 }; 136 137 smsc911x_pins: pinmux_smsc911x_pins { 138 pinctrl-single,pins = < 139 OMAP3_CORE1_IOPAD(0x21d2, PIN_INPUT | MUX_MODE4) /* mcspi1_cs2.gpio_176 */ 140 >; 141 }; 142}; 143 144&omap3_pmx_wkup { 145 dss_dpi_pins2: pinmux_dss_dpi_pins1 { 146 pinctrl-single,pins = < 147 OMAP3_WKUP_IOPAD(0x2a0a, PIN_OUTPUT | MUX_MODE3) /* sys_boot0.dss_data18 */ 148 OMAP3_WKUP_IOPAD(0x2a0c, PIN_OUTPUT | MUX_MODE3) /* sys_boot1.dss_data19 */ 149 OMAP3_WKUP_IOPAD(0x2a10, PIN_OUTPUT | MUX_MODE3) /* sys_boot3.dss_data20 */ 150 OMAP3_WKUP_IOPAD(0x2a12, PIN_OUTPUT | MUX_MODE3) /* sys_boot4.dss_data21 */ 151 OMAP3_WKUP_IOPAD(0x2a14, PIN_OUTPUT | MUX_MODE3) /* sys_boot5.dss_data22 */ 152 OMAP3_WKUP_IOPAD(0x2a16, PIN_OUTPUT | MUX_MODE3) /* sys_boot6.dss_data23 */ 153 >; 154 }; 155}; 156 157&mmc1 { 158 pinctrl-names = "default"; 159 pinctrl-0 = <&mmc1_pins>; 160}; 161 162&mmc2 { 163 pinctrl-names = "default"; 164 pinctrl-0 = <&mmc2_pins>; 165}; 166 167&mmc3 { 168 status = "disabled"; 169}; 170 171&uart1 { 172 interrupts-extended = <&intc 72 &omap3_pmx_core OMAP3_UART1_RX>; 173}; 174 175&uart2 { 176 interrupts-extended = <&intc 73 &omap3_pmx_core OMAP3_UART2_RX>; 177}; 178 179&uart3 { 180 interrupts-extended = <&intc 74 &omap3_pmx_core OMAP3_UART3_RX>; 181 pinctrl-names = "default"; 182 pinctrl-0 = <&uart3_pins>; 183}; 184 185/* 186 * GPIO_61 (nUSB2_EN_1V8) must be low to enable on-board EHCI USB2 interface 187 * for bus switch SN74CB3Q3384A, level-shifter SN74AVC16T245DGGR, and 1.8V. 188 */ 189&gpio2 { 190 en_usb2_port { 191 gpio-hog; 192 gpios = <29 GPIO_ACTIVE_HIGH>; /* gpio_61 */ 193 output-low; 194 line-name = "enable usb2 port"; 195 }; 196}; 197 198/* T2_GPIO_2 low to route GPIO_61 to on-board devices */ 199&twl_gpio { 200 en_on_board_gpio_61 { 201 gpio-hog; 202 gpios = <2 GPIO_ACTIVE_HIGH>; 203 output-low; 204 line-name = "en_hsusb2_clk"; 205 }; 206}; 207 208&gpmc { 209 ranges = <0 0 0x30000000 0x1000000>, /* CS0: 16MB for NAND */ 210 <5 0 0x2c000000 0x01000000>; /* CS5: 16MB for LAN9220 */ 211 212 ethernet@gpmc { 213 pinctrl-names = "default"; 214 pinctrl-0 = <&smsc911x_pins>; 215 }; 216}; 217