Searched refs:sse3 (Results 1 – 25 of 172) sorted by relevance
1234567
1 ; RUN: llc < %s -mtriple=i386-apple-darwin -mattr=-avx,+sse3 | FileCheck %s5 …%res = call <2 x double> @llvm.x86.sse3.addsub.pd(<2 x double> %a0, <2 x double> %a1) ; <<2 x doub…8 declare <2 x double> @llvm.x86.sse3.addsub.pd(<2 x double>, <2 x double>) nounwind readnone13 …%res = call <4 x float> @llvm.x86.sse3.addsub.ps(<4 x float> %a0, <4 x float> %a1) ; <<4 x float>>…16 declare <4 x float> @llvm.x86.sse3.addsub.ps(<4 x float>, <4 x float>) nounwind readnone21 …%res = call <2 x double> @llvm.x86.sse3.hadd.pd(<2 x double> %a0, <2 x double> %a1) ; <<2 x double…24 declare <2 x double> @llvm.x86.sse3.hadd.pd(<2 x double>, <2 x double>) nounwind readnone29 …%res = call <4 x float> @llvm.x86.sse3.hadd.ps(<4 x float> %a0, <4 x float> %a1) ; <<4 x float>> […32 declare <4 x float> @llvm.x86.sse3.hadd.ps(<4 x float>, <4 x float>) nounwind readnone37 …%res = call <2 x double> @llvm.x86.sse3.hsub.pd(<2 x double> %a0, <2 x double> %a1) ; <<2 x double…[all …]
2 ; RUN: llc < %s -fast-isel -mtriple=i386-unknown-unknown -mattr=+sse3 | FileCheck %s --check-prefix…3 ; RUN: llc < %s -fast-isel -mtriple=x86_64-unknown-unknown -mattr=+sse3 | FileCheck %s --check-pref…5 ; NOTE: This should use IR equivalent to what is generated by clang/test/CodeGen/sse3-builtins.c17 %res = call <2 x double> @llvm.x86.sse3.addsub.pd(<2 x double> %a0, <2 x double> %a1)20 declare <2 x double> @llvm.x86.sse3.addsub.pd(<2 x double>, <2 x double>) nounwind readnone32 %res = call <4 x float> @llvm.x86.sse3.addsub.ps(<4 x float> %a0, <4 x float> %a1)35 declare <4 x float> @llvm.x86.sse3.addsub.ps(<4 x float>, <4 x float>) nounwind readnone47 %res = call <2 x double> @llvm.x86.sse3.hadd.pd(<2 x double> %a0, <2 x double> %a1)50 declare <2 x double> @llvm.x86.sse3.hadd.pd(<2 x double>, <2 x double>) nounwind readnone62 %res = call <4 x float> @llvm.x86.sse3.hadd.ps(<4 x float> %a0, <4 x float> %a1)[all …]
1 ; RUN: llc < %s -mtriple=x86_64-linux -mattr=+sse3 | FileCheck %s2 ; RUN: llc < %s -mtriple=x86_64-win32 -mattr=+sse3 | FileCheck %s -check-prefix=WIN6416 tail call void @llvm.x86.sse3.monitor(i8* %P, i32 %E, i32 %H)20 declare void @llvm.x86.sse3.monitor(i8*, i32, i32) nounwind31 tail call void @llvm.x86.sse3.mwait(i32 %E, i32 %H)35 declare void @llvm.x86.sse3.mwait(i32, i32) nounwind
1 ; RUN: llc < %s -mtriple=x86_64-linux -mattr=+64bit,+sse3 -print-failed-fuse-candidates -regalloc=b…18 declare <4 x float> @llvm.x86.sse3.addsub.ps(<4 x float>, <4 x float>)19 declare <4 x float> @llvm.x86.sse3.hadd.ps(<4 x float>, <4 x float>)20 declare <4 x float> @llvm.x86.sse3.hsub.ps(<4 x float>, <4 x float>)25 declare <2 x double> @llvm.x86.sse3.addsub.pd(<2 x double>, <2 x double>)26 declare <2 x double> @llvm.x86.sse3.hadd.pd(<2 x double>, <2 x double>)27 declare <2 x double> @llvm.x86.sse3.hsub.pd(<2 x double>, <2 x double>)71 %t = call <4 x float> @llvm.x86.sse3.addsub.ps(<4 x float> %y, <4 x float> %f)76 %t = call <4 x float> @llvm.x86.sse3.hadd.ps(<4 x float> %y, <4 x float> %f)81 %t = call <4 x float> @llvm.x86.sse3.hsub.ps(<4 x float> %y, <4 x float> %f)[all …]
2 ; RUN: llc < %s -mtriple=i686-apple-macosx -mattr=-sse,-sse2,-sse3 -enable-unsafe-fp-math | FileCh…3 ; RUN: llc < %s -mtriple=i686-apple-macosx -mattr=-sse,-sse2,-sse3 -enable-unsafe-fp-math | FileCh…4 ; RUN: llc < %s -mtriple=i686-apple-macosx -mattr=-sse,-sse2,-sse3 | FileCheck %s --check-prefix=SA…
10 ; RUN: llc < %s -march=x86-64 -mcpu=k8-sse3 | FileCheck %s11 ; RUN: llc < %s -march=x86-64 -mcpu=opteron-sse3 | FileCheck %s12 ; RUN: llc < %s -march=x86-64 -mcpu=athlon64-sse3 | FileCheck %s
21 ; RUN: llc < %s -mtriple=i386-pc-windows-msvc -mattr=+sse3 | FileCheck %s --check-prefix=CHECK …22 ; RUN: llc < %s -mtriple=i386-unknown-linux-gnu -mattr=+sse3 | FileCheck %s --check-prefix=CHECK …23 ; RUN: llc < %s -mtriple=x86_64-pc-windows-msvc -mattr=+sse3 | FileCheck %s --check-prefix=CHECK …24 ; RUN: llc < %s -mtriple=x86_64-unknown-linux-gnu -mattr=+sse3 | FileCheck %s --check-prefix=CHECK …
2 ; RUN: llc < %s -mtriple=i686-apple-macosx -mattr=-sse2,-sse3,-sse | FileCheck %s3 ; RUN: llc < %s -mtriple=i686-apple-macosx -mattr=-sse,-sse2,-sse3 -enable-unsafe-fp-math -enable-n…
2 ; RUN: llc < %s -mtriple=i386-apple-darwin -mattr=+sse3 -show-mc-encoding | FileCheck %s --check-pr…5 ; RUN: llc < %s -mtriple=x86_64-apple-darwin -mattr=+sse3 -show-mc-encoding | FileCheck %s --check-…19 …%res = call <2 x double> @llvm.x86.sse3.addsub.pd(<2 x double> %a0, <2 x double> %a1) ; <<2 x doub…22 declare <2 x double> @llvm.x86.sse3.addsub.pd(<2 x double>, <2 x double>) nounwind readnone35 …%res = call <4 x float> @llvm.x86.sse3.addsub.ps(<4 x float> %a0, <4 x float> %a1) ; <<4 x float>>…38 declare <4 x float> @llvm.x86.sse3.addsub.ps(<4 x float>, <4 x float>) nounwind readnone51 …%res = call <2 x double> @llvm.x86.sse3.hadd.pd(<2 x double> %a0, <2 x double> %a1) ; <<2 x double…54 declare <2 x double> @llvm.x86.sse3.hadd.pd(<2 x double>, <2 x double>) nounwind readnone67 …%res = call <4 x float> @llvm.x86.sse3.hadd.ps(<4 x float> %a0, <4 x float> %a1) ; <<4 x float>> […70 declare <4 x float> @llvm.x86.sse3.hadd.ps(<4 x float>, <4 x float>) nounwind readnone[all …]
2 ; RUN: llc < %s -fast-isel -mtriple=i386-unknown-unknown -mattr=+sse3 | FileCheck %s --check-prefix…5 ; RUN: llc < %s -fast-isel -mtriple=x86_64-unknown-unknown -mattr=+sse3 | FileCheck %s --check-pref…9 ; NOTE: This should use IR equivalent to what is generated by clang/test/CodeGen/sse3-builtins.c21 %res = call <2 x double> @llvm.x86.sse3.addsub.pd(<2 x double> %a0, <2 x double> %a1)24 declare <2 x double> @llvm.x86.sse3.addsub.pd(<2 x double>, <2 x double>) nounwind readnone36 %res = call <4 x float> @llvm.x86.sse3.addsub.ps(<4 x float> %a0, <4 x float> %a1)39 declare <4 x float> @llvm.x86.sse3.addsub.ps(<4 x float>, <4 x float>) nounwind readnone51 %res = call <2 x double> @llvm.x86.sse3.hadd.pd(<2 x double> %a0, <2 x double> %a1)54 declare <2 x double> @llvm.x86.sse3.hadd.pd(<2 x double>, <2 x double>) nounwind readnone66 %res = call <4 x float> @llvm.x86.sse3.hadd.ps(<4 x float> %a0, <4 x float> %a1)[all …]
2 ; RUN: llc < %s -mtriple=i686-linux -mattr=+sse3 | FileCheck %s -check-prefixes=CHECK,X863 ; RUN: llc < %s -mtriple=x86_64-linux -mattr=+sse3 | FileCheck %s -check-prefixes=CHECK,X644 ; RUN: llc < %s -mtriple=x86_64-win32 -mattr=+sse3 | FileCheck %s -check-prefixes=CHECK,WIN6433 tail call void @llvm.x86.sse3.monitor(i8* %P, i32 %E, i32 %H)37 declare void @llvm.x86.sse3.monitor(i8*, i32, i32) nounwind60 tail call void @llvm.x86.sse3.mwait(i32 %E, i32 %H)64 declare void @llvm.x86.sse3.mwait(i32, i32) nounwind
11 …tures"="+avx,+avx2,+avx512bw,+avx512f,+f16c,+fma,+mmx,+popcnt,+sse,+sse2,+sse3,+sse4.1,+sse4.2,+ss…12 …tures"="+avx,+avx2,+avx512f,+avx512vl,+f16c,+fma,+mmx,+popcnt,+sse,+sse2,+sse3,+sse4.1,+sse4.2,+ss…
10 ; RUN: llc < %s -mtriple=x86_64-- -mcpu=k8-sse3 | FileCheck %s11 ; RUN: llc < %s -mtriple=x86_64-- -mcpu=opteron-sse3 | FileCheck %s12 ; RUN: llc < %s -mtriple=x86_64-- -mcpu=athlon64-sse3 | FileCheck %s
19 %1 = call <4 x float> @llvm.x86.sse3.hadd.ps(<4 x float> %a0, <4 x float> %a1)20 %2 = call <4 x float> @llvm.x86.sse3.hadd.ps(<4 x float> %a2, <4 x float> %a3)35 %1 = call <2 x double> @llvm.x86.sse3.hadd.pd(<2 x double> %a0, <2 x double> %a1)36 %2 = call <2 x double> @llvm.x86.sse3.hadd.pd(<2 x double> %a2, <2 x double> %a3)51 %1 = call <2 x double> @llvm.x86.sse3.hsub.pd(<2 x double> %a0, <2 x double> %a1)52 %2 = call <2 x double> @llvm.x86.sse3.hsub.pd(<2 x double> %a2, <2 x double> %a3)67 %1 = call <4 x float> @llvm.x86.sse3.hsub.ps(<4 x float> %a0, <4 x float> %a1)68 %2 = call <4 x float> @llvm.x86.sse3.hsub.ps(<4 x float> %a2, <4 x float> %a3)397 declare <4 x float> @llvm.x86.sse3.hadd.ps(<4 x float>, <4 x float>)398 declare <4 x float> @llvm.x86.sse3.hsub.ps(<4 x float>, <4 x float>)[all …]
2 ; RUN: llc < %s -mtriple=i686-unknown-unknown -mattr=-sse,-sse2,-sse3 …3 ; RUN: llc < %s -mtriple=i686-unknown-unknown -mattr=-sse,-sse2,-sse3 -enable-unsafe-fp-math -enabl…
16 tail call void @llvm.x86.sse3.monitor(i8* %P, i32 %E, i32 %H)20 declare void @llvm.x86.sse3.monitor(i8*, i32, i32) nounwind31 tail call void @llvm.x86.sse3.mwait(i32 %E, i32 %H)35 declare void @llvm.x86.sse3.mwait(i32, i32) nounwind
2 ; RUN: llc < %s -march=x86 -mattr=-sse2,-sse3,-sse | grep fabs\$ | \4 ; RUN: llc < %s -march=x86 -mattr=-sse,-sse2,-sse3 -enable-unsafe-fp-math -enable-no-nans-fp-math |…
2 ; RUN: llc < %s -march=x86 -mattr=-sse,-sse2,-sse3 -enable-unsafe-fp-math | \4 ; RUN: llc < %s -march=x86 -mattr=-sse,-sse2,-sse3 -enable-unsafe-fp-math | \
128 info->ia32.sse3 = (flags_ecx & FLAC__CPUINFO_IA32_CPUID_SSE3 ) ? true : false; in ia32_cpu_info()146 dfprintf(stderr, " SSE3 ....... %c\n", info->ia32.sse3 ? 'Y' : 'n'); in ia32_cpu_info()189 info->x86.sse3 = (flags_ecx & FLAC__CPUINFO_IA32_CPUID_SSE3 ) ? true : false; in x86_64_cpu_info()203 dfprintf(stderr, " SSE3 ....... %c\n", info->x86.sse3 ? 'Y' : 'n'); in x86_64_cpu_info()
78 { "sse3", "Enable SSE3 instructions", X86::FeatureSSE3, X86::FeatureSSE2 },96 …{ "athlon64-sse3", "Select the athlon64-sse3 processor", X86::FeatureSSE3 | X86::Feature3DNowA | X…116 …{ "k8-sse3", "Select the k8-sse3 processor", X86::FeatureSSE3 | X86::Feature3DNowA | X86::FeatureC…120 …{ "opteron-sse3", "Select the opteron-sse3 processor", X86::FeatureSSE3 | X86::Feature3DNowA | X86…
28 %call = call <16 x i8> @llvm.x86.sse3.ldu.dq(i8* %p)32 declare <16 x i8> @llvm.x86.sse3.ldu.dq(i8* %p) nounwind39 ; CHECK: call <16 x i8> @llvm.x86.sse3.ldu.dq
149 FLAC__bool sse3; member161 FLAC__bool sse3; member
90 explicit module sse3 {96 export sse3111 export sse3