1; RUN: llc < %s -mtriple=x86_64-- -mcpu=athlon | FileCheck %s 2; RUN: llc < %s -mtriple=x86_64-- -mcpu=athlon-tbird | FileCheck %s 3; RUN: llc < %s -mtriple=x86_64-- -mcpu=athlon-4 | FileCheck %s 4; RUN: llc < %s -mtriple=x86_64-- -mcpu=athlon-xp | FileCheck %s 5; RUN: llc < %s -mtriple=x86_64-- -mcpu=athlon-mp | FileCheck %s 6; RUN: llc < %s -mtriple=x86_64-- -mcpu=k8 | FileCheck %s 7; RUN: llc < %s -mtriple=x86_64-- -mcpu=opteron | FileCheck %s 8; RUN: llc < %s -mtriple=x86_64-- -mcpu=athlon64 | FileCheck %s 9; RUN: llc < %s -mtriple=x86_64-- -mcpu=athlon-fx | FileCheck %s 10; RUN: llc < %s -mtriple=x86_64-- -mcpu=k8-sse3 | FileCheck %s 11; RUN: llc < %s -mtriple=x86_64-- -mcpu=opteron-sse3 | FileCheck %s 12; RUN: llc < %s -mtriple=x86_64-- -mcpu=athlon64-sse3 | FileCheck %s 13; RUN: llc < %s -mtriple=x86_64-- -mcpu=amdfam10 | FileCheck %s 14; RUN: llc < %s -mtriple=x86_64-- -mcpu=btver1 | FileCheck %s 15; RUN: llc < %s -mtriple=x86_64-- -mcpu=btver2 | FileCheck %s 16; RUN: llc < %s -mtriple=x86_64-- -mcpu=bdver1 | FileCheck %s 17; RUN: llc < %s -mtriple=x86_64-- -mcpu=bdver2 | FileCheck %s 18; RUN: llc < %s -mtriple=x86_64-- -mcpu=bdver3 | FileCheck %s 19; RUN: llc < %s -mtriple=x86_64-- -mcpu=bdver4 | FileCheck %s 20; RUN: llc < %s -mtriple=x86_64-- -mcpu=znver1 | FileCheck %s 21 22; Verify that for the X86_64 processors that are known to have poor latency 23; double precision shift instructions we do not generate 'shld' or 'shrd' 24; instructions. 25 26;uint64_t lshift(uint64_t a, uint64_t b, int c) 27;{ 28; return (a << c) | (b >> (64-c)); 29;} 30 31define i64 @lshift(i64 %a, i64 %b, i32 %c) nounwind readnone { 32entry: 33; CHECK-NOT: shld 34 %sh_prom = zext i32 %c to i64 35 %shl = shl i64 %a, %sh_prom 36 %sub = sub nsw i32 64, %c 37 %sh_prom1 = zext i32 %sub to i64 38 %shr = lshr i64 %b, %sh_prom1 39 %or = or i64 %shr, %shl 40 ret i64 %or 41} 42 43;uint64_t rshift(uint64_t a, uint64_t b, int c) 44;{ 45; return (a >> c) | (b << (64-c)); 46;} 47 48define i64 @rshift(i64 %a, i64 %b, i32 %c) nounwind readnone { 49entry: 50; CHECK-NOT: shrd 51 %sh_prom = zext i32 %c to i64 52 %shr = lshr i64 %a, %sh_prom 53 %sub = sub nsw i32 64, %c 54 %sh_prom1 = zext i32 %sub to i64 55 %shl = shl i64 %b, %sh_prom1 56 %or = or i64 %shl, %shr 57 ret i64 %or 58} 59 60 61