/external/swiftshader/third_party/subzero/tests_lit/assembler/arm32/ |
D | ldrex-strex.ll | 88 ; ***** Example of strexh ***** 89 ; ASM: strexh r4, r3, [r2]
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/external/llvm/test/MC/ARM/ |
D | thumbv8m.s | 83 strexh r1, r2, [r3] label
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D | basic-arm-instructions.s | 2864 strexh r4, r2, [r5] 2869 @ CHECK: strexh r4, r2, [r5] @ encoding: [0x92,0x4f,0xe5,0xe1]
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D | basic-thumb2-instructions.s | 2907 strexh r9, r7, [r12] 2914 @ CHECK: strexh r9, r7, [r12] @ encoding: [0xcc,0xe8,0x59,0x7f]
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/external/swiftshader/third_party/llvm-7.0/llvm/test/MC/ARM/ |
D | thumbv8m.s | 83 strexh r1, r2, [r3] label
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D | basic-arm-instructions.s | 2866 strexh r4, r2, [r5] 2871 @ CHECK: strexh r4, r2, [r5] @ encoding: [0x92,0x4f,0xe5,0xe1]
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D | basic-thumb2-instructions.s | 2955 strexh r9, r7, [r12] 2962 @ CHECK: strexh r9, r7, [r12] @ encoding: [0xcc,0xe8,0x59,0x7f]
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/external/llvm/test/CodeGen/ARM/ |
D | cmpxchg-O0.ll | 35 ; CHECK: strexh [[STATUS:r[0-9]+]], r2, [r0]
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D | ldstrex.ll | 78 ; CHECK: strexh r0, r1, [r2]
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D | atomic-ops-v8.ll | 47 ; CHECK-NEXT: strexh [[STATUS:r[0-9]+]], [[NEW]], [r[[ADDR]]] 239 ; CHECK-NEXT: strexh [[STATUS:r[0-9]+]], [[NEW]], [r[[ADDR]]] 335 ; CHECK-NEXT: strexh [[STATUS:r[0-9]+]], [[NEW]], [r[[ADDR]]] 735 ; CHECK-NEXT: strexh [[STATUS:r[0-9]+]], r[[OLDX]], [r[[ADDR]]] 848 ; CHECK-NEXT: strexh [[STATUS:r[0-9]+]], r[[NEW]], {{.*}}[[ADDR]] 961 ; CHECK-NEXT: strexh [[STATUS:r[0-9]+]], r[[NEW]], {{.*}}[[ADDR]]
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/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/ARM/ |
D | cmpxchg-O0.ll | 38 ; CHECK: strexh [[STATUS:r[0-9]+]], r2, [r0]
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D | atomic-ops-v8.ll | 47 ; CHECK-NEXT: strexh [[STATUS:r[0-9]+]], [[NEW]], [r[[ADDR]]] 239 ; CHECK-NEXT: strexh [[STATUS:r[0-9]+]], [[NEW]], [r[[ADDR]]] 335 ; CHECK-NEXT: strexh [[STATUS:r[0-9]+]], [[NEW]], [r[[ADDR]]] 735 ; CHECK-NEXT: strexh [[STATUS:r[0-9]+]], r[[OLDX]], [r[[ADDR]]] 848 ; CHECK-NEXT: strexh [[STATUS:r[0-9]+]], r[[NEW]], {{.*}}[[ADDR]] 961 ; CHECK-NEXT: strexh [[STATUS:r[0-9]+]], r[[NEW]], {{.*}}[[ADDR]]
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D | ldstrex.ll | 78 ; CHECK: strexh r0, r1, [r2]
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/external/swiftshader/third_party/subzero/tests_lit/llvm2ice_tests/ |
D | nacl-atomic-intrinsics.ll | 391 ; ARM32: strexh 670 ; ARM32: strexh 881 ; ARM32: strexh 923 ; ARM32: strexh 1120 ; ARM32: strexh 1290 ; ARM32: strexh 1450 ; ARM32: strexh
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/external/v8/src/compiler/arm/ |
D | code-generator-arm.cc | 2692 ASSEMBLE_ATOMIC_EXCHANGE_INTEGER(ldrexh, strexh); in AssembleArchInstruction() 2697 ASSEMBLE_ATOMIC_EXCHANGE_INTEGER(ldrexh, strexh); in AssembleArchInstruction() 2723 ASSEMBLE_ATOMIC_COMPARE_EXCHANGE_INTEGER(ldrexh, strexh, in AssembleArchInstruction() 2731 ASSEMBLE_ATOMIC_COMPARE_EXCHANGE_INTEGER(ldrexh, strexh, in AssembleArchInstruction() 2753 ASSEMBLE_ATOMIC_BINOP(ldrexh, strexh, inst); \ in AssembleArchInstruction() 2758 ASSEMBLE_ATOMIC_BINOP(ldrexh, strexh, inst); \ in AssembleArchInstruction()
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/external/v8/src/arm/ |
D | assembler-arm.h | 932 void strexh(Register src1, Register src2, Register dst, Condition cond = al);
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/external/capstone/suite/MC/ARM/ |
D | basic-arm-instructions.s.cs | 812 0x92,0x4f,0xe5,0xe1 = strexh r4, r2, [r5]
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D | basic-thumb2-instructions.s.cs | 936 0xcc,0xe8,0x59,0x7f = strexh r9, r7, [r12]
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/external/swiftshader/third_party/LLVM/test/MC/ARM/ |
D | basic-arm-instructions.s | 2048 strexh r4, r2, [r5] 2053 @ CHECK: strexh r4, r2, [r5] @ encoding: [0x92,0x4f,0xe5,0xe1]
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D | basic-thumb2-instructions.s | 2430 strexh r9, r7, [r12] 2437 @ CHECK: strexh r9, r7, [r12] @ encoding: [0xcc,0xe8,0x59,0x7f]
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/external/vixl/src/aarch32/ |
D | assembler-aarch32.h | 3474 void strexh(Condition cond, 3478 void strexh(Register rd, Register rt, const MemOperand& operand) { in strexh() function 3479 strexh(al, rd, rt, operand); in strexh()
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D | disasm-aarch32.h | 1298 void strexh(Condition cond,
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/external/swiftshader/third_party/LLVM/test/MC/Disassembler/ARM/ |
D | basic-arm-instructions.txt | 1790 # CHECK: strexh r4, r2, [r5
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D | thumb2.txt | 1807 # CHECK: strexh r9, r7, [r12]
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/external/swiftshader/third_party/llvm-7.0/llvm/test/MC/Disassembler/ARM/ |
D | basic-arm-instructions.txt | 1942 # CHECK: strexh r4, r2, [r5
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