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Searched refs:stw (Results 1 – 25 of 315) sorted by relevance

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/external/u-boot/arch/nios2/cpu/
Dexceptions.S24 stw r0, 0(sp)
25 stw r1, 4(sp)
26 stw r2, 8(sp)
27 stw r3, 12(sp)
28 stw r4, 16(sp)
29 stw r5, 20(sp)
30 stw r6, 24(sp)
31 stw r7, 28(sp)
32 stw r8, 32(sp)
33 stw r9, 36(sp)
[all …]
/external/u-boot/examples/standalone/
Dppc_setjmp.S26 stw r1,(JB_GPR1*4)(3)
28 stw r2,(JB_GPR2*4)(3)
29 stw r14,((JB_GPRS+0)*4)(3)
31 stw r0,(JB_LR*4)(3)
32 stw r15,((JB_GPRS+1)*4)(3)
35 stw r16,((JB_GPRS+2)*4)(3)
37 stw r0,(JB_CR*4)(3)
38 stw r17,((JB_GPRS+3)*4)(3)
40 stw r18,((JB_GPRS+4)*4)(3)
42 stw r19,((JB_GPRS+5)*4)(3)
[all …]
/external/swiftshader/third_party/LLVM/test/CodeGen/PowerPC/
Dppc32-vaarg.ll20 ; CHECK-NEXT: stw 3, -4(1)
21 ; CHECK-NEXT: stw 6, -8(1)
22 ; CHECK-NEXT: stw 4, -12(1)
23 ; CHECK-NEXT: stw 5, -16(1)
27 ; CHECK-NEXT: stw 3, -8(1)
39 ; CHECK-NEXT: stw 0, -20(1)
40 ; CHECK-NEXT: stw 5, -24(1)
41 ; CHECK-NEXT: stw 3, -28(1)
42 ; CHECK-NEXT: stw 7, -32(1)
43 ; CHECK-NEXT: stw 8, -36(1)
[all …]
/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/PowerPC/
D2008-10-28-f128-i32.ll8 ; CHECK-NEXT: stw 0, 4(1)
11 ; CHECK-NEXT: stw 29, 412(1) # 4-byte Folded Spill
12 ; CHECK-NEXT: stw 30, 416(1) # 4-byte Folded Spill
14 ; CHECK-NEXT: stw 12, 408(1)
27 ; CHECK-NEXT: stw 4, 396(1)
30 ; CHECK-NEXT: stw 4, 392(1)
32 ; CHECK-NEXT: stw 4, 404(1)
34 ; CHECK-NEXT: stw 3, 400(1)
47 ; CHECK-NEXT: stw 29, 340(1)
48 ; CHECK-NEXT: stw 3, 336(1)
[all …]
Dtls_get_addr_clobbers.ll27 ; CHECK-DAG: stw 3, 0([[BACKUP_3]])
28 ; CHECK-DAG: stw 3, 0([[BACKUP_4]])
29 ; CHECK-DAG: stw 3, 0([[BACKUP_5]])
30 ; CHECK-DAG: stw 3, 0([[BACKUP_6]])
31 ; CHECK-DAG: stw 3, 0([[BACKUP_7]])
32 ; CHECK-DAG: stw 3, 0([[BACKUP_8]])
33 ; CHECK-DAG: stw 3, 0([[BACKUP_9]])
34 ; CHECK-DAG: stw 3, 0([[BACKUP_10]])
Di32-to-float.ll22 ; CHECK-PWR6: stw 3,
29 ; CHECK-A2: stw 3,
35 ; CHECK-VSX: stw 3,
54 ; CHECK-PWR6: stw 3,
60 ; CHECK-A2: stw 3,
66 ; CHECK-VSX: stw 3,
78 ; CHECK-A2: stw 3,
84 ; CHECK-VSX: stw 3,
96 ; CHECK-A2: stw 3,
102 ; CHECK-VSX: stw 3,
/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/XCore/
Dllvm-intrinsics.ll33 ; CHECK: stw lr, sp[0]
107 ; CHECK: stw r4, sp[4]
109 ; CHECK: stw r5, sp[3]
158 ; CHECKFP: stw r10, sp[1]
160 ; CHECKFP: stw r4, r10[9]
161 ; CHECKFP: stw r5, r10[8]
162 ; CHECKFP: stw r6, r10[7]
163 ; CHECKFP: stw r7, r10[6]
164 ; CHECKFP: stw r8, r10[5]
165 ; CHECKFP: stw r9, r10[4]
[all …]
Dvarargs.ll7 ; CHECK: stw r[[REG:[0-3]{1,1}]]
9 ; CHECK: stw r[[REG:[0-3]{1,1}]]
11 ; CHECK: stw r[[REG:[0-3]{1,1}]]
13 ; CHECK: stw r[[REG:[0-3]{1,1}]]
28 ; CHECK: stw lr, sp[1]
29 ; CHECK-DAG: stw r3, sp[6]
30 ; CHECK-DAG: stw r0, sp[3]
31 ; CHECK-DAG: stw r1, sp[4]
32 ; CHECK-DAG: stw r2, sp[5]
34 ; CHECK: stw r0, sp[2]
[all …]
Dbigstructret.ll27 ; CHECK-NEXT: stw [[REGISTER]], sp[2]
41 ; CHECK: stw [[REGISTER]], sp[1]
65 ; CHECK: stw r1, r0[4]
67 ; CHECK: stw r1, r0[3]
69 ; CHECK: stw r1, r0[2]
71 ; CHECK: stw r1, r0[1]
73 ; CHECK: stw r1, r0[0]
/external/llvm/test/CodeGen/XCore/
Dllvm-intrinsics.ll33 ; CHECK: stw lr, sp[0]
107 ; CHECK: stw r4, sp[4]
109 ; CHECK: stw r5, sp[3]
158 ; CHECKFP: stw r10, sp[1]
160 ; CHECKFP: stw r4, r10[9]
161 ; CHECKFP: stw r5, r10[8]
162 ; CHECKFP: stw r6, r10[7]
163 ; CHECKFP: stw r7, r10[6]
164 ; CHECKFP: stw r8, r10[5]
165 ; CHECKFP: stw r9, r10[4]
[all …]
Dvarargs.ll7 ; CHECK: stw r[[REG:[0-3]{1,1}]]
9 ; CHECK: stw r[[REG:[0-3]{1,1}]]
11 ; CHECK: stw r[[REG:[0-3]{1,1}]]
13 ; CHECK: stw r[[REG:[0-3]{1,1}]]
28 ; CHECK: stw lr, sp[1]
29 ; CHECK: stw r0, sp[3]
30 ; CHECK: stw r1, sp[4]
31 ; CHECK: stw r2, sp[5]
32 ; CHECK: stw r3, sp[6]
34 ; CHECK: stw r0, sp[2]
[all …]
Dbigstructret.ll27 ; CHECK-NEXT: stw [[REGISTER]], sp[2]
41 ; CHECK: stw [[REGISTER]], sp[1]
65 ; CHECK: stw r1, r0[4]
67 ; CHECK: stw r1, r0[3]
69 ; CHECK: stw r1, r0[2]
71 ; CHECK: stw r1, r0[1]
73 ; CHECK: stw r1, r0[0]
/external/libunwind_llvm/src/
DUnwindRegistersSave.S566 stw r0, 8(r3)
568 stw r0, 0(r3) ; store lr as ssr0
569 stw r1, 12(r3)
570 stw r2, 16(r3)
571 stw r3, 20(r3)
572 stw r4, 24(r3)
573 stw r5, 28(r3)
574 stw r6, 32(r3)
575 stw r7, 36(r3)
576 stw r8, 40(r3)
[all …]
/external/u-boot/post/lib_powerpc/
Dasm.S77 stw r3, 0(r4)
97 stw r3, 0(r4)
124 stw r0, 0(r4)
126 stw r3, 0(r4)
155 stw r0, 0(r4)
157 stw r3, 0(r4)
179 stw r3, 0(r4)
200 stw r3, 0(r4)
222 stw r3, 0(r4)
224 stw r5, 0(r4)
[all …]
/external/python/cpython2/Modules/_ctypes/libffi/src/powerpc/
Dsysv.S45 stw %r28,-16(%r8)
47 stw %r29,-12(%r8)
49 stw %r30, -8(%r8)
51 stw %r31, -4(%r8)
53 stw %r9, 4(%r8)
111 stw %r3,0(%r30)
113 stw %r4,4(%r30)
116 stw %r5,8(%r30)
117 stw %r6,12(%r30)
150 stw %r3, 0(%r30)
[all …]
/external/libffi/src/powerpc/
Dsysv.S45 stw %r28,-16(%r8)
47 stw %r29,-12(%r8)
49 stw %r30, -8(%r8)
51 stw %r31, -4(%r8)
53 stw %r9, 4(%r8)
111 stw %r3,0(%r30)
113 stw %r4,4(%r30)
116 stw %r5,8(%r30)
117 stw %r6,12(%r30)
150 stw %r3, 0(%r30)
[all …]
/external/python/cpython2/Modules/_ctypes/libffi/src/nios2/
Dsysv.S49 stw ra, 8(sp)
50 stw fp, 4(sp)
51 stw r16, 0(sp)
110 stw ra, 0(sp)
112 stw r4, 4(sp)
114 stw r5, 8(sp)
116 stw r6, 12(sp)
118 stw r7, 16(sp)
/external/libffi/src/nios2/
Dsysv.S49 stw ra, 8(sp)
50 stw fp, 4(sp)
51 stw r16, 0(sp)
110 stw ra, 0(sp)
112 stw r4, 4(sp)
114 stw r5, 8(sp)
116 stw r6, 12(sp)
118 stw r7, 16(sp)
/external/llvm/test/CodeGen/PowerPC/
Dtls_get_addr_clobbers.ll27 ; CHECK-DAG: stw 3, 0([[BACKUP_3]])
28 ; CHECK-DAG: stw 3, 0([[BACKUP_4]])
29 ; CHECK-DAG: stw 3, 0([[BACKUP_5]])
30 ; CHECK-DAG: stw 3, 0([[BACKUP_6]])
31 ; CHECK-DAG: stw 3, 0([[BACKUP_7]])
32 ; CHECK-DAG: stw 3, 0([[BACKUP_8]])
33 ; CHECK-DAG: stw 3, 0([[BACKUP_9]])
34 ; CHECK-DAG: stw 3, 0([[BACKUP_10]])
Di32-to-float.ll22 ; CHECK-PWR6: stw 3,
29 ; CHECK-A2: stw 3,
35 ; CHECK-VSX: stw 3,
54 ; CHECK-PWR6: stw 3,
60 ; CHECK-A2: stw 3,
66 ; CHECK-VSX: stw 3,
78 ; CHECK-A2: stw 3,
84 ; CHECK-VSX: stw 3,
96 ; CHECK-A2: stw 3,
102 ; CHECK-VSX: stw 3,
/external/u-boot/include/
Dppc_asm.tmpl139 #define SAVE_GPR(n, base) stw n,GPR0+4*(n)(base)
169 stw r20,_CCR(r21); /* save registers */ \
170 stw r22,GPR22(r21); \
171 stw r23,GPR23(r21); \
173 stw r20,GPR20(r21); \
175 stw r22,GPR21(r21); \
177 stw r20,_LINK(r21); \
179 stw r22,_CTR(r21); \
181 stw r20,_XER(r21); \
183 stw r20,_DAR(r21); \
[all …]
/external/libffi/src/pa/
Dlinux.S52 stw %rp, -20(%sp)
73 stw %r4, 12(%r3)
78 stw %arg3, -48(%r3) /* save flags; we need it later */
113 stw %ret0, 0(%r20)
137 stw %ret0, 0(%r20)
139 stw %ret1, 4(%r20)
266 stw %rp, -20(%sp)
275 stw %arg0, -36(%r3)
276 stw %arg1, -40(%r3)
277 stw %arg2, -44(%r3)
[all …]
/external/python/cpython2/Modules/_ctypes/libffi/src/pa/
Dlinux.S52 stw %rp, -20(%sp)
73 stw %r4, 12(%r3)
78 stw %arg3, -48(%r3) /* save flags; we need it later */
113 stw %ret0, 0(%r20)
137 stw %ret0, 0(%r20)
139 stw %ret1, 4(%r20)
266 stw %rp, -20(%sp)
275 stw %arg0, -36(%r3)
276 stw %arg1, -40(%r3)
277 stw %arg2, -44(%r3)
[all …]
/external/swiftshader/third_party/LLVM/test/CodeGen/XCore/
Dbigstructret.ll34 ; CHECK: stw r1, r0[4]
36 ; CHECK: stw r1, r0[3]
38 ; CHECK: stw r1, r0[2]
40 ; CHECK: stw r1, r0[1]
42 ; CHECK: stw r1, r0[0]
D2011-08-01-VarargsBug.ll6 ; CHECK: stw r[[REG:[0-3]{1,1}]]
8 ; CHECK: stw r[[REG:[0-3]{1,1}]]
10 ; CHECK: stw r[[REG:[0-3]{1,1}]]
12 ; CHECK: stw r[[REG:[0-3]{1,1}]]

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