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/external/icu/icu4c/source/samples/
DMakefile.in75 subtarget=`echo $@ | sed s/-samples-recursive//`; \
77 echo "$(MAKE)[$(MAKELEVEL)]: Making \`$$subtarget' in \`$$subdir'"; \
80 local_target="$$subtarget-local"; \
82 local_target="$$subtarget"; \
87 $(MAKE) "$$subtarget-local" || exit; \
/external/python/cpython2/Lib/plat-mac/lib-scriptpackages/CodeWarrior/
DCodeWarrior_suite.py322 class subtarget(aetools.ComponentItem): class
334 subtargets = subtarget
520 subtarget._superclassnames = ['target']
521 subtarget._privpropdict = {
526 subtarget._privelemdict = {
567 'subtarget' : subtarget,
639 'SBTG' : subtarget,
D__init__.py69 getbaseclasses(subtarget)
136 'SBTG' : subtarget,
/external/llvm/include/llvm/Target/
DTargetSchedule.td27 // each subtarget, define WriteRes and ReadAdvance to associate
31 // subtarget, define ItinRW entries to map ItineraryClass to
33 // be subtarget specific and can be directly associated with resources
36 // C. In the subtarget, map SchedReadWrite types to specific
39 // subtarget can directly associate resources with SchedReadWrite
42 // D. In either the target or subtarget, define SchedWriteVariant or
95 // and may actually be generated for that subtarget must clear this
264 // defined by the subtarget, and maps the SchedWrite to processor
268 // be used instead to define subtarget specific SchedWrites and map
270 // itinerary classes to the subtarget's SchedWrites.
[all …]
/external/swiftshader/third_party/llvm-7.0/llvm/test/MC/ARM/
Dfixup-per-fragment.s3 @ The relaxations should be applied using the subtarget from the fragment
4 @ containing the fixup and not the per module subtarget.
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/SystemZ/
DSystemZ.td17 // SystemZ subtarget features
23 // SystemZ subtarget scheduling models
/external/swiftshader/third_party/llvm-7.0/llvm/include/llvm/Target/
DTargetSchedule.td27 // each subtarget, define WriteRes and ReadAdvance to associate
31 // subtarget, define ItinRW entries to map ItineraryClass to
33 // be subtarget specific and can be directly associated with resources
36 // C. In the subtarget, map SchedReadWrite types to specific
39 // subtarget can directly associate resources with SchedReadWrite
42 // D. In either the target or subtarget, define SchedWriteVariant or
95 // and may actually be generated for that subtarget must clear this
273 // defined by the subtarget, and maps the SchedWrite to processor
277 // be used instead to define subtarget specific SchedWrites and map
279 // itinerary classes to the subtarget's SchedWrites.
[all …]
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Sparc/
DLeonFeatures.td18 //support to casa instruction; for leon3 subtarget only
32 //support to casa instruction; for leon3 subtarget only
/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/ARM/
Ddivmod-hwdiv.ll1 ; The hwdiv subtarget feature should only influence thumb, not arm.
7 ; The hwdiv-arm subtarget feature should only influence arm, not thumb.
/external/swiftshader/third_party/llvm-7.0/llvm/test/MC/Disassembler/AMDGPU/
Dsi-support.txt3 # CHECK: LLVM ERROR: Disassembly not yet supported for subtarget
/external/llvm/docs/CommandGuide/
Dtblgen.rst108 .. option:: -gen-subtarget
110 Generate subtarget enumerations.
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AMDGPU/
DCMakeLists.txt16 tablegen(LLVM AMDGPUGenSubtargetInfo.inc -gen-subtarget)
29 tablegen(LLVM R600GenSubtargetInfo.inc -gen-subtarget)
/external/llvm/lib/Target/Sparc/
DLeonFeatures.td18 // support to casa instruction; for leon3 subtarget only
27 // support to casa instruction; for leon3 subtarget only
/external/swiftshader/third_party/llvm-7.0/llvm/test/MC/X86/AlignedBundling/
Dbundle-subtarget-change-error.s4 # Switching mode will change subtarget, which we can't do within a bundle
/external/swiftshader/third_party/LLVM/docs/CommandGuide/
Dtblgen.pod92 =item B<-gen-subtarget>
94 Generate subtarget enumerations.
/external/swiftshader/third_party/llvm-7.0/llvm/docs/CommandGuide/
Dtblgen.rst113 .. option:: -gen-subtarget
115 Generate subtarget enumerations.
/external/llvm/lib/Target/AVR/
DCMakeLists.txt6 tablegen(LLVM AVRGenSubtargetInfo.inc -gen-subtarget)
/external/llvm/test/CodeGen/AMDGPU/
Dread-register-invalid-subtarget.ll3 ; CHECK: invalid register "flat_scratch_lo" for subtarget.
Dllvm.amdgcn.log.clamp.ll4 ; ERR: intrinsic not supported on subtarget
/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/AMDGPU/
Dread-register-invalid-subtarget.ll3 ; CHECK: invalid register "flat_scratch_lo" for subtarget.
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/MSP430/
DCMakeLists.txt8 tablegen(LLVM MSP430GenSubtargetInfo.inc -gen-subtarget)
/external/llvm/lib/Target/MSP430/
DCMakeLists.txt8 tablegen(LLVM MSP430GenSubtargetInfo.inc -gen-subtarget)
/external/swiftshader/third_party/LLVM/lib/Target/CellSPU/
DSPURegisterInfo.h37 SPURegisterInfo(const SPUSubtarget &subtarget, const TargetInstrInfo &tii);
/external/llvm/lib/Target/ARM/
DARMSchedule.td12 // Here we define the subtarget independent read/write per-operand resources.
13 // The subtarget schedule definitions will then map these to the subtarget's
41 // Next, the subtarget td file assigns resources to the abstract resources
/external/llvm/lib/Target/BPF/
DCMakeLists.txt10 tablegen(LLVM BPFGenSubtargetInfo.inc -gen-subtarget)

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