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Searched refs:umin (Results 1 – 25 of 222) sorted by relevance

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/external/swiftshader/third_party/llvm-7.0/llvm/test/MC/AArch64/SVE/
Dumin.s10 umin z0.b, z0.b, #0 label
16 umin z31.b, z31.b, #255 label
22 umin z0.b, z0.b, #0 label
28 umin z31.b, z31.b, #255 label
34 umin z0.b, z0.b, #0 label
40 umin z31.b, z31.b, #255 label
46 umin z0.b, z0.b, #0 label
52 umin z31.b, z31.b, #255 label
58 umin z31.b, p7/m, z31.b, z31.b label
64 umin z31.h, p7/m, z31.h, z31.h label
[all …]
Dumin-diagnostics.s3 umin z0.b, z0.b, #-1 label
8 umin z31.b, z31.b, #256 label
13 umin z0.b, p8/m, z0.b, z0.b label
23 umin z31.b, z31.b, #255 label
/external/llvm/test/CodeGen/AMDGPU/
Dumed3.ll119 define internal i32 @umin(i32 %x, i32 %y) #2 {
176 %tmp0 = call i32 @umin(i32 %x, i32 %y)
178 %tmp2 = call i32 @umin(i32 %tmp1, i32 %z)
188 %tmp0 = call i32 @umin(i32 %x, i32 %y)
190 %tmp2 = call i32 @umin(i32 %tmp1, i32 %z)
200 %tmp0 = call i32 @umin(i32 %x, i32 %y)
202 %tmp2 = call i32 @umin(i32 %z, i32 %tmp1)
212 %tmp0 = call i32 @umin(i32 %x, i32 %y)
214 %tmp2 = call i32 @umin(i32 %z, i32 %tmp1)
224 %tmp0 = call i32 @umin(i32 %y, i32 %x)
[all …]
/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/AMDGPU/
Dumed3.ll121 define internal i32 @umin(i32 %x, i32 %y) #2 {
178 %tmp0 = call i32 @umin(i32 %x, i32 %y)
180 %tmp2 = call i32 @umin(i32 %tmp1, i32 %z)
190 %tmp0 = call i32 @umin(i32 %x, i32 %y)
192 %tmp2 = call i32 @umin(i32 %tmp1, i32 %z)
202 %tmp0 = call i32 @umin(i32 %x, i32 %y)
204 %tmp2 = call i32 @umin(i32 %z, i32 %tmp1)
214 %tmp0 = call i32 @umin(i32 %x, i32 %y)
216 %tmp2 = call i32 @umin(i32 %z, i32 %tmp1)
226 %tmp0 = call i32 @umin(i32 %y, i32 %x)
[all …]
/external/swiftshader/third_party/llvm-7.0/llvm/test/Analysis/CostModel/AArch64/
Dvector-reduce.ll49 ; COST-LABEL: umin.i8.v8i8
50 …ost of 157 for instruction: %r = call i8 @llvm.experimental.vector.reduce.umin.i8.v8i8(<8 x i8> %v)
51 ; CODE-LABEL: umin.i8.v8i8
53 define i8 @umin.i8.v8i8(<8 x i8> %v) {
54 %r = call i8 @llvm.experimental.vector.reduce.umin.i8.v8i8(<8 x i8> %v)
58 ; COST-LABEL: umin.i8.v16i8
59 …ost of 388 for instruction: %r = call i8 @llvm.experimental.vector.reduce.umin.i8.v16i8(<16 x i8> …
60 ; CODE-LABEL: umin.i8.v16i8
62 define i8 @umin.i8.v16i8(<16 x i8> %v) {
63 %r = call i8 @llvm.experimental.vector.reduce.umin.i8.v16i8(<16 x i8> %v)
[all …]
/external/capstone/suite/MC/AArch64/
Dneon-max-min.s.cs20 0x20,0x6c,0x22,0x2e = umin v0.8b, v1.8b, v2.8b
21 0x20,0x6c,0x22,0x6e = umin v0.16b, v1.16b, v2.16b
22 0x20,0x6c,0x62,0x2e = umin v0.4h, v1.4h, v2.4h
23 0x20,0x6c,0x62,0x6e = umin v0.8h, v1.8h, v2.8h
24 0x20,0x6c,0xa2,0x2e = umin v0.2s, v1.2s, v2.2s
25 0x20,0x6c,0xa2,0x6e = umin v0.4s, v1.4s, v2.4s
/external/llvm/test/MC/AArch64/
Dneon-max-min.s53 umin v0.8b, v1.8b, v2.8b
54 umin v0.16b, v1.16b, v2.16b
55 umin v0.4h, v1.4h, v2.4h
56 umin v0.8h, v1.8h, v2.8h
57 umin v0.2s, v1.2s, v2.2s
58 umin v0.4s, v1.4s, v2.4s
/external/swiftshader/third_party/llvm-7.0/llvm/test/MC/AArch64/
Dneon-max-min.s53 umin v0.8b, v1.8b, v2.8b
54 umin v0.16b, v1.16b, v2.16b
55 umin v0.4h, v1.4h, v2.4h
56 umin v0.8h, v1.8h, v2.8h
57 umin v0.2s, v1.2s, v2.2s
58 umin v0.4s, v1.4s, v2.4s
/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/AArch64/
Daarch64-minmaxv.ll15 declare i8 @llvm.experimental.vector.reduce.umin.i8.v16i8(<16 x i8>)
16 declare i16 @llvm.experimental.vector.reduce.umin.i16.v8i16(<8 x i16>)
17 declare i32 @llvm.experimental.vector.reduce.umin.i32.v4i32(<4 x i32>)
98 %r = call i8 @llvm.experimental.vector.reduce.umin.i8.v16i8(<16 x i8> %arr.load)
106 %r = call i16 @llvm.experimental.vector.reduce.umin.i16.v8i16(<8 x i16> %arr.load)
114 %r = call i32 @llvm.experimental.vector.reduce.umin.i32.v4i32(<4 x i32> %arr.load)
158 declare i16 @llvm.experimental.vector.reduce.umin.i16.v16i16(<16 x i16>)
162 ; CHECK: umin [[V0:v[0-9]+]].8h, {{v[0-9]+}}.8h, {{v[0-9]+}}.8h
165 %r = call i16 @llvm.experimental.vector.reduce.umin.i16.v16i16(<16 x i16> %arr.load)
169 declare i32 @llvm.experimental.vector.reduce.umin.i32.v16i32(<16 x i32>)
[all …]
Dminmax.ll28 ; CHECK: umin
52 ; CHECK: umin
68 ; CHECK: umin
99 ; CHECK-NOT: umin
100 ; The icmp is used by two instructions, so don't produce a umin node.
Dminmax-of-minmax.ll6 ; 4 min/max flavors (smin/smax/umin/umax) *
525 ; CHECK-NEXT: umin v0.4s, v0.4s, v1.4s
526 ; CHECK-NEXT: umin v1.4s, v1.4s, v2.4s
527 ; CHECK-NEXT: umin v0.4s, v0.4s, v1.4s
541 ; CHECK-NEXT: umin v0.4s, v0.4s, v1.4s
542 ; CHECK-NEXT: umin v1.4s, v2.4s, v1.4s
543 ; CHECK-NEXT: umin v0.4s, v0.4s, v1.4s
557 ; CHECK-NEXT: umin v2.4s, v1.4s, v2.4s
558 ; CHECK-NEXT: umin v0.4s, v0.4s, v1.4s
559 ; CHECK-NEXT: umin v0.4s, v2.4s, v0.4s
[all …]
Darm64-vmax.ll188 ;CHECK: umin.8b
191 %tmp3 = call <8 x i8> @llvm.aarch64.neon.umin.v8i8(<8 x i8> %tmp1, <8 x i8> %tmp2)
197 ;CHECK: umin.16b
200 %tmp3 = call <16 x i8> @llvm.aarch64.neon.umin.v16i8(<16 x i8> %tmp1, <16 x i8> %tmp2)
206 ;CHECK: umin.4h
209 %tmp3 = call <4 x i16> @llvm.aarch64.neon.umin.v4i16(<4 x i16> %tmp1, <4 x i16> %tmp2)
215 ;CHECK: umin.8h
218 %tmp3 = call <8 x i16> @llvm.aarch64.neon.umin.v8i16(<8 x i16> %tmp1, <8 x i16> %tmp2)
224 ;CHECK: umin.2s
227 %tmp3 = call <2 x i32> @llvm.aarch64.neon.umin.v2i32(<2 x i32> %tmp1, <2 x i32> %tmp2)
[all …]
/external/llvm/test/Transforms/IndVarSimplify/
Dbackedge-on-min-max.ll235 %umin.cmp = icmp ult i32 %a_len, %n
236 %umin = select i1 %umin.cmp, i32 %a_len, i32 %n
237 %entry.cond = icmp ult i32 5, %umin
253 %be.cond = icmp ult i32 %idx.inc, %umin
263 %umin.cmp = icmp ult i32 %a_len, %n
264 %umin = select i1 %umin.cmp, i32 %a_len, i32 %n
265 %entry.cond = icmp ult i32 5, %umin
281 %be.cond = icmp ult i32 %idx.inc, %umin
291 %umin.cmp = icmp ult i32 42, %n
292 %umin = select i1 %umin.cmp, i32 42, i32 %n
[all …]
/external/swiftshader/third_party/llvm-7.0/llvm/test/Transforms/IndVarSimplify/
Dbackedge-on-min-max.ll235 %umin.cmp = icmp ult i32 %a_len, %n
236 %umin = select i1 %umin.cmp, i32 %a_len, i32 %n
237 %entry.cond = icmp ult i32 5, %umin
253 %be.cond = icmp ult i32 %idx.inc, %umin
263 %umin.cmp = icmp ult i32 %a_len, %n
264 %umin = select i1 %umin.cmp, i32 %a_len, i32 %n
265 %entry.cond = icmp ult i32 5, %umin
281 %be.cond = icmp ult i32 %idx.inc, %umin
291 %umin.cmp = icmp ult i32 42, %n
292 %umin = select i1 %umin.cmp, i32 42, i32 %n
[all …]
/external/llvm/test/CodeGen/AArch64/
Dminmax.ll28 ; CHECK: umin
52 ; CHECK: umin
68 ; CHECK: umin
99 ; CHECK-NOT: umin
100 ; The icmp is used by two instructions, so don't produce a umin node.
Darm64-vmax.ll188 ;CHECK: umin.8b
191 %tmp3 = call <8 x i8> @llvm.aarch64.neon.umin.v8i8(<8 x i8> %tmp1, <8 x i8> %tmp2)
197 ;CHECK: umin.16b
200 %tmp3 = call <16 x i8> @llvm.aarch64.neon.umin.v16i8(<16 x i8> %tmp1, <16 x i8> %tmp2)
206 ;CHECK: umin.4h
209 %tmp3 = call <4 x i16> @llvm.aarch64.neon.umin.v4i16(<4 x i16> %tmp1, <4 x i16> %tmp2)
215 ;CHECK: umin.8h
218 %tmp3 = call <8 x i16> @llvm.aarch64.neon.umin.v8i16(<8 x i16> %tmp1, <8 x i16> %tmp2)
224 ;CHECK: umin.2s
227 %tmp3 = call <2 x i32> @llvm.aarch64.neon.umin.v2i32(<2 x i32> %tmp1, <2 x i32> %tmp2)
[all …]
/external/llvm/unittests/IR/
DConstantRangeTest.cpp454 EXPECT_EQ(Full.umin(Full), Full); in TEST_F()
455 EXPECT_EQ(Full.umin(Empty), Empty); in TEST_F()
456 EXPECT_EQ(Full.umin(Some), ConstantRange(APInt(16, 0), APInt(16, 0xaaa))); in TEST_F()
457 EXPECT_EQ(Full.umin(Wrap), Full); in TEST_F()
458 EXPECT_EQ(Empty.umin(Empty), Empty); in TEST_F()
459 EXPECT_EQ(Empty.umin(Some), Empty); in TEST_F()
460 EXPECT_EQ(Empty.umin(Wrap), Empty); in TEST_F()
461 EXPECT_EQ(Empty.umin(One), Empty); in TEST_F()
462 EXPECT_EQ(Some.umin(Some), Some); in TEST_F()
463 EXPECT_EQ(Some.umin(Wrap), ConstantRange(APInt(16, 0), APInt(16, 0xaaa))); in TEST_F()
[all …]
/external/swiftshader/third_party/llvm-7.0/llvm/test/Transforms/InstCombine/
Dumin-icmp.ll4 ; If we have a umin feeding an unsigned or equality icmp that shares an
5 ; operand with the umin, the compare should always be folded.
11 ; umin(X, Y) == X --> X <= Y
67 ; umin(X, Y) >= X --> X <= Y
123 ; umin(X, Y) != X --> X > Y
179 ; umin(X, Y) < X --> X > Y
/external/deqp-deps/glslang/Test/
D300BuiltIns.frag4 uint umax, umin;
43 uvec4 uv10 = clamp(uv4y, umin, umax);
/external/swiftshader/third_party/llvm-7.0/llvm/unittests/IR/
DConstantRangeTest.cpp511 EXPECT_EQ(Full.umin(Full), Full); in TEST_F()
512 EXPECT_EQ(Full.umin(Empty), Empty); in TEST_F()
513 EXPECT_EQ(Full.umin(Some), ConstantRange(APInt(16, 0), APInt(16, 0xaaa))); in TEST_F()
514 EXPECT_EQ(Full.umin(Wrap), Full); in TEST_F()
515 EXPECT_EQ(Empty.umin(Empty), Empty); in TEST_F()
516 EXPECT_EQ(Empty.umin(Some), Empty); in TEST_F()
517 EXPECT_EQ(Empty.umin(Wrap), Empty); in TEST_F()
518 EXPECT_EQ(Empty.umin(One), Empty); in TEST_F()
519 EXPECT_EQ(Some.umin(Some), Some); in TEST_F()
520 EXPECT_EQ(Some.umin(Wrap), ConstantRange(APInt(16, 0), APInt(16, 0xaaa))); in TEST_F()
[all …]
/external/llvm/lib/IR/
DConstantRange.cpp783 ConstantRange::umin(const ConstantRange &Other) const { in umin() function in ConstantRange
788 APInt NewL = APIntOps::umin(getUnsignedMin(), Other.getUnsignedMin()); in umin()
789 APInt NewU = APIntOps::umin(getUnsignedMax(), Other.getUnsignedMax()) + 1; in umin()
831 APInt umin = APIntOps::umin(Other.getUnsignedMax(), getUnsignedMax()); in binaryAnd() local
832 if (umin.isAllOnesValue()) in binaryAnd()
834 return ConstantRange(APInt::getNullValue(getBitWidth()), umin + 1); in binaryAnd()
/external/llvm/test/CodeGen/ARM/
Datomic-op.ll124 %11 = atomicrmw umin i32* %val2, i32 16 monotonic
133 %12 = atomicrmw umin i32* %val2, i32 %uneg monotonic
166 %0 = atomicrmw umin i16* %val, i16 16 monotonic
175 %1 = atomicrmw umin i16* %val, i16 %uneg monotonic
207 %0 = atomicrmw umin i8* %val, i8 16 monotonic
216 %1 = atomicrmw umin i8* %val, i8 %uneg monotonic
/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/PowerPC/
Datomic-minmax.ll35 %0 = atomicrmw umin i32* %minimum, i32 %val monotonic
91 %0 = atomicrmw umin i16* %minimum, i16 %val monotonic
147 %0 = atomicrmw umin i8* %minimum, i8 %val monotonic
203 %0 = atomicrmw umin i64* %minimum, i64 %val monotonic
285 %0 = atomicrmw umin i16* %minimum, i16 %val monotonic
387 %0 = atomicrmw umin i8* %minimum, i8 %val monotonic
/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/X86/
Dvector-reduce-umin.ll81 %1 = call i64 @llvm.experimental.vector.reduce.umin.i64.v2i64(<2 x i64> %a0)
214 %1 = call i64 @llvm.experimental.vector.reduce.umin.i64.v4i64(<4 x i64> %a0)
409 %1 = call i64 @llvm.experimental.vector.reduce.umin.i64.v8i64(<8 x i64> %a0)
745 %1 = call i64 @llvm.experimental.vector.reduce.umin.i64.v16i64(<16 x i64> %a0)
803 %1 = call i32 @llvm.experimental.vector.reduce.umin.i32.v4i32(<4 x i32> %a0)
884 %1 = call i32 @llvm.experimental.vector.reduce.umin.i32.v8i32(<8 x i32> %a0)
989 %1 = call i32 @llvm.experimental.vector.reduce.umin.i32.v16i32(<16 x i32> %a0)
1139 %1 = call i32 @llvm.experimental.vector.reduce.umin.i32.v32i32(<32 x i32> %a0)
1191 %1 = call i16 @llvm.experimental.vector.reduce.umin.i16.v8i16(<8 x i16> %a0)
1260 %1 = call i16 @llvm.experimental.vector.reduce.umin.i16.v16i16(<16 x i16> %a0)
[all …]
/external/libhevc/common/arm64/
Dihevc_deblk_luma_horz.s232 umin v18.8b, v20.8b , v30.8b
248 umin v18.8b, v21.8b , v16.8b
283 umin v18.8b, v19.8b , v30.8b
309 umin v18.8b, v20.8b , v30.8b
397 umin v18.8b, v21.8b , v16.8b
423 umin v18.8b, v19.8b , v30.8b

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