| /external/llvm/lib/Target/Hexagon/ |
| D | HexagonIntrinsicsV60.td | 124 def : Pat <(v1024i1 (bitconvert (v32i32 VectorRegs128B:$src1))),
125 (v1024i1 (V6_vandvrt_128B(v32i32 VectorRegs128B:$src1),
129 def : Pat <(v1024i1 (bitconvert (v64i16 VectorRegs128B:$src1))),
130 (v1024i1 (V6_vandvrt_128B(v64i16 VectorRegs128B:$src1),
134 def : Pat <(v1024i1 (bitconvert (v128i8 VectorRegs128B:$src1))),
135 (v1024i1 (V6_vandvrt_128B(v128i8 VectorRegs128B:$src1),
139 def : Pat <(v1024i1 (bitconvert (v16i64 VectorRegs128B:$src1))),
140 (v1024i1 (V6_vandvrt_128B(v16i64 VectorRegs128B:$src1),
144 def : Pat <(v32i32 (bitconvert (v1024i1 VecPredRegs128B:$src1))),
145 (v32i32 (V6_vandqrt_128B(v1024i1 VecPredRegs128B:$src1),
[all …]
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| D | HexagonISelLowering.cpp | 204 LocVT == MVT::v128i8 || LocVT == MVT::v1024i1) { in CC_Hexagon_VarArg()
372 LocVT == MVT::v128i8 || LocVT == MVT::v1024i1)) { in CC_HexagonVector()
420 (LocVT == MVT::v1024i1 && UseHVX && UseHVXDbl)) { in RetCC_Hexagon()
549 ty == MVT::v512i1 || ty == MVT::v1024i1); in IsHvxVectorType()
1146 } else if (RegVT == MVT::v512i1 || RegVT == MVT::v1024i1) { in LowerFormalArguments()
1773 addRegisterClass(MVT::v1024i1, &Hexagon::VecPredRegs128BRegClass); in HexagonTargetLowering()
2871 case MVT::v1024i1: in getRegForInlineAsmConstraint()
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| D | HexagonRegisterInfo.td | 244 def VecPredRegs128B : RegisterClass<"Hexagon", [v1024i1], 1024,
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Hexagon/ |
| D | HexagonIntrinsicsV60.td | 47 def : Pat <(v1024i1 (bitconvert (v32i32 HvxVR:$src1))),
48 (v1024i1 (V6_vandvrt (v32i32 HvxVR:$src1), (A2_tfrsi 0x01010101)))>;
50 def : Pat <(v1024i1 (bitconvert (v64i16 HvxVR:$src1))),
51 (v1024i1 (V6_vandvrt (v64i16 HvxVR:$src1), (A2_tfrsi 0x01010101)))>;
53 def : Pat <(v1024i1 (bitconvert (v128i8 HvxVR:$src1))),
54 (v1024i1 (V6_vandvrt (v128i8 HvxVR:$src1), (A2_tfrsi 0x01010101)))>;
56 def : Pat <(v32i32 (bitconvert (v1024i1 HvxQR:$src1))),
57 (v32i32 (V6_vandqrt (v1024i1 HvxQR:$src1), (A2_tfrsi 0x01010101)))>;
59 def : Pat <(v64i16 (bitconvert (v1024i1 HvxQR:$src1))),
60 (v64i16 (V6_vandqrt (v1024i1 HvxQR:$src1), (A2_tfrsi 0x01010101)))>;
[all …]
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| D | HexagonRegisterInfo.td | 274 [v512i1, v1024i1, v512i1]>;
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| D | HexagonISelDAGToDAGHVX.cpp | 2149 SDVTList VTs = CurDAG->getVTList(MVT::v32i32, MVT::v1024i1); in SelectHVXDualOutput()
2163 SDVTList VTs = CurDAG->getVTList(MVT::v32i32, MVT::v1024i1); in SelectHVXDualOutput()
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| D | HexagonISelLoweringHVX.cpp | 54 addRegisterClass(MVT::v1024i1, &Hexagon::HvxQRRegClass); in initializeHVXLowering()
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| /external/llvm/include/llvm/CodeGen/ |
| D | MachineValueType.h | 66 v1024i1 = 20, // 1024 x i1 enumerator
272 return (SimpleTy == MVT::v1024i1 || SimpleTy == MVT::v128i8 || in is1024BitVector()
324 case v1024i1: return i1; in getVectorElementType()
375 case v1024i1: return 1024; in getVectorNumElements()
503 case v1024i1: in getSizeInBits()
600 if (NumElements == 1024) return MVT::v1024i1; in getVectorVT()
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| D | ValueTypes.td | 43 def v1024i1: ValueType<1024,20>; //1024 x i1 vector value
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| /external/swiftshader/third_party/llvm-7.0/llvm/include/llvm/Support/ |
| D | MachineValueType.h | 69 v1024i1 = 23, // 1024 x i1 enumerator
376 return (SimpleTy == MVT::v1024i1 || SimpleTy == MVT::v128i8 || in is1024BitVector()
429 case v1024i1: in getVectorElementType()
522 case v1024i1: return 1024; in getVectorNumElements()
739 case v1024i1: in getSizeInBits()
841 if (NumElements == 1024) return MVT::v1024i1; in getVectorVT()
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/CodeGen/ |
| D | ValueTypes.cpp | 149 case MVT::v1024i1: return "v1024i1"; in getEVTString()
230 case MVT::v1024i1: return VectorType::get(Type::getInt1Ty(Context), 1024); in getTypeForEVT()
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| /external/llvm/lib/IR/ |
| D | ValueTypes.cpp | 152 case MVT::v1024i1: return "v1024i1"; in getEVTString()
230 case MVT::v1024i1: return VectorType::get(Type::getInt1Ty(Context), 1024); in getTypeForEVT()
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| /external/swiftshader/third_party/llvm-7.0/llvm/include/llvm/CodeGen/ |
| D | ValueTypes.td | 45 def v1024i1: ValueType<1024,23>; //1024 x i1 vector value
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| /external/llvm/utils/TableGen/ |
| D | CodeGenTarget.cpp | 80 case MVT::v1024i1: return "MVT::v1024i1"; in getEnumName()
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| /external/swiftshader/third_party/llvm-7.0/llvm/utils/TableGen/ |
| D | CodeGenTarget.cpp | 88 case MVT::v1024i1: return "MVT::v1024i1"; in getEnumName()
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| /external/llvm/include/llvm/IR/ |
| D | Intrinsics.td | 176 def llvm_v1024i1_ty : LLVMType<v1024i1>; //1024 x i1
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| /external/swiftshader/third_party/llvm-7.0/llvm/include/llvm/IR/ |
| D | Intrinsics.td | 204 def llvm_v1024i1_ty : LLVMType<v1024i1>; //1024 x i1
|