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/external/swiftshader/third_party/subzero/src/
DIceTypes.def49 X(v16i1, 4, 1, 16, i1, "<16 x i1>", "v16i1") \
77 X(v16i1, 1, 1, 0, 0, 1, 1, v16i1) \
78 X(v16i8, 1, 1, 0, 1, 0, 1, v16i1) \
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/X86/
DX86InstrVecCompiler.td326 def maskzeroupperv16i1 : maskzeroupper<v16i1, VK16>;
358 def : Pat<(v16i1 (insert_subvector (v16i1 immAllZerosV),
361 def : Pat<(v16i1 (insert_subvector (v16i1 immAllZerosV),
382 def : Pat<(v16i1 (insert_subvector (v16i1 immAllZerosV),
385 def : Pat<(v16i1 (insert_subvector (v16i1 immAllZerosV),
408 def : Pat<(v16i1 (insert_subvector (v16i1 immAllZerosV),
413 def : Pat<(v16i1 (insert_subvector (v16i1 immAllZerosV),
418 def : Pat<(v16i1 (insert_subvector (v16i1 immAllZerosV),
425 def : Pat<(v16i1 (insert_subvector (v16i1 immAllZerosV),
432 def : Pat<(v16i1 (insert_subvector (v16i1 immAllZerosV),
[all …]
DX86CallingConv.td85 // Promote v8i1/v16i1/v32i1 arguments to i32.
86 CCIfType<[v8i1, v16i1, v32i1], CCPromoteToType<i32>>,
158 // Promote v16i1 arguments to i16.
159 CCIfType<[v16i1], CCPromoteToType<i16>>,
229 CCIfType<[v16i1], CCPromoteToType<v16i8>>,
530 CCIfType<[v16i1], CCPromoteToType<v16i8>>,
806 CCIfType<[v16i1], CCPromoteToType<v16i8>>,
979 CCIfType<[v16i1, v8i1], CCAssignToReg<[K1]>>,
/external/llvm/include/llvm/CodeGen/
DMachineValueType.h62 v16i1 = 16, // 16 x i1 enumerator
229 SimpleTy == MVT::v16i1); in is16BitVector()
320 case v16i1: in getVectorElementType()
389 case v16i1: in getVectorNumElements()
456 case v16i1: in getSizeInBits()
596 if (NumElements == 16) return MVT::v16i1; in getVectorVT()
DValueTypes.td39 def v16i1 : ValueType<16, 16>; // 16 x i1 vector value
/external/swiftshader/third_party/subzero/crosstest/
Dtest_select_main.cpp145 testSelect<v16si8, v16i1>(TotalTests, Passes, Failures); in main()
146 testSelect<v16ui8, v16i1>(TotalTests, Passes, Failures); in main()
149 testSelectI1<v16i1>(TotalTests, Passes, Failures); in main()
Dtest_vector_ops_main.cpp175 testInsertElement<v16i1>(TotalTests, Passes, Failures); in main()
186 testExtractElement<v16i1>(TotalTests, Passes, Failures); in main()
197 testShuffleVector<v16i1>(TotalTests, Passes, Failures); in main()
Dtest_vector_ops.def31 X(v16i1, v16ui8, 16) \
Dvectors.def32 X(v16i1, v16si8, 16)
/external/swiftshader/third_party/llvm-7.0/llvm/include/llvm/Support/
DMachineValueType.h64 v16i1 = 18, // 16 x i1 enumerator
332 SimpleTy == MVT::v16i1); in is16BitVector()
424 case v16i1: in getVectorElementType()
542 case v16i1: in getVectorNumElements()
657 case v16i1: in getSizeInBits()
836 if (NumElements == 16) return MVT::v16i1; in getVectorVT()
/external/llvm/lib/Target/AArch64/
DAArch64TargetTransformInfo.cpp446 { ISD::SELECT, MVT::v16i1, MVT::v16i16, 16 }, in getCmpSelInstrCost()
448 { ISD::SELECT, MVT::v16i1, MVT::v16i32, 16 }, in getCmpSelInstrCost()
451 { ISD::SELECT, MVT::v16i1, MVT::v16i64, 16 * AmortizationCost } in getCmpSelInstrCost()
/external/swiftshader/third_party/llvm-7.0/llvm/lib/CodeGen/
DValueTypes.cpp144 case MVT::v16i1: return "v16i1"; in getEVTString()
225 case MVT::v16i1: return VectorType::get(Type::getInt1Ty(Context), 16); in getTypeForEVT()
/external/llvm/lib/IR/
DValueTypes.cpp148 case MVT::v16i1: return "v16i1"; in getEVTString()
226 case MVT::v16i1: return VectorType::get(Type::getInt1Ty(Context), 16); in getTypeForEVT()
/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/X86/
Davx512-vselect.ll28 ; v16i1 masks in the select during type legalization, and in so doing extend them
/external/llvm/test/CodeGen/SystemZ/
Dvec-move-16.ll5 ; Test a v16i1->v16i8 extension.
Dvec-move-15.ll5 ; Test a v16i1->v16i8 extension.
Dvec-move-17.ll5 ; Test a v16i8->v16i1 truncation.
Dvec-and-03.ll5 ; Test a v16i1->v16i8 extension.
/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/SystemZ/
Dvec-move-15.ll5 ; Test a v16i1->v16i8 extension.
Dvec-move-16.ll5 ; Test a v16i1->v16i8 extension.
Dvec-and-03.ll5 ; Test a v16i1->v16i8 extension.
Dvec-move-17.ll5 ; Test a v16i8->v16i1 truncation.
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AArch64/
DAArch64TargetTransformInfo.cpp600 { ISD::SELECT, MVT::v16i1, MVT::v16i16, 16 }, in getCmpSelInstrCost()
602 { ISD::SELECT, MVT::v16i1, MVT::v16i32, 16 }, in getCmpSelInstrCost()
605 { ISD::SELECT, MVT::v16i1, MVT::v16i64, 16 * AmortizationCost } in getCmpSelInstrCost()
/external/swiftshader/third_party/llvm-7.0/configs/common/lib/Target/X86/
DX86GenGlobalISel.inc2559 …1] } (KANDNWrr:{ *:[v16i1] } (COPY_TO_REGCLASS:{ *:[v16i1] } VK1:{ *:[v1i1] }:$src1, VK16:{ *:[i32…
2593 …1] } (KANDNWrr:{ *:[v16i1] } (COPY_TO_REGCLASS:{ *:[v16i1] } VK1:{ *:[v1i1] }:$src1, VK16:{ *:[i32…
2621 …i1] } (KANDWrr:{ *:[v16i1] } (COPY_TO_REGCLASS:{ *:[v16i1] } VK1:{ *:[v1i1] }:$src1, VK16:{ *:[i32…
3514 …i1] } (KANDWrr:{ *:[v16i1] } (COPY_TO_REGCLASS:{ *:[v16i1] } VK2:{ *:[v2i1] }:$src1, VK16:{ *:[i32…
3587 …i1] } (KANDWrr:{ *:[v16i1] } (COPY_TO_REGCLASS:{ *:[v16i1] } VK4:{ *:[v4i1] }:$src1, VK16:{ *:[i32…
3670 …i1] } (KANDWrr:{ *:[v16i1] } (COPY_TO_REGCLASS:{ *:[v16i1] } VK8:{ *:[v8i1] }:$src1, VK16:{ *:[i32…
3721 … (and:{ *:[v16i1] } VK16:{ *:[v16i1] }:$src1, VK16:{ *:[v16i1] }:$src2) => (KANDWrr:{ *:[v16i1] …
3783 …1i1] } (KORWrr:{ *:[v16i1] } (COPY_TO_REGCLASS:{ *:[v16i1] } VK1:{ *:[v1i1] }:$src1, VK16:{ *:[i32…
4592 …2i1] } (KORWrr:{ *:[v16i1] } (COPY_TO_REGCLASS:{ *:[v16i1] } VK2:{ *:[v2i1] }:$src1, VK16:{ *:[i32…
4665 …4i1] } (KORWrr:{ *:[v16i1] } (COPY_TO_REGCLASS:{ *:[v16i1] } VK4:{ *:[v4i1] }:$src1, VK16:{ *:[i32…
[all …]
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Hexagon/
DHexagonRegisterInfo.td294 [v16i1, v32i1, v16i1]>;

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