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Searched refs:v16i16 (Results 1 – 25 of 108) sorted by relevance

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/external/clang/test/CodeGen/
Dppc64-vector.c8 typedef short v16i16 __attribute__((vector_size (32))); typedef
10 struct v16i16 { v16i16 x; }; struct
43 v16i16 test_v16i16(v16i16 x) in test_v16i16()
49 struct v16i16 test_struct_v16i16(struct v16i16 x) in test_struct_v16i16()
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/X86/
DX86TargetTransformInfo.cpp332 { ISD::SDIV, MVT::v16i16, 6 }, // vpmulhw sequence in getArithmeticInstrCost()
333 { ISD::SREM, MVT::v16i16, 8 }, // vpmulhw+mul+sub sequence in getArithmeticInstrCost()
334 { ISD::UDIV, MVT::v16i16, 6 }, // vpmulhuw sequence in getArithmeticInstrCost()
335 { ISD::UREM, MVT::v16i16, 8 }, // vpmulhuw+mul+sub sequence in getArithmeticInstrCost()
358 { ISD::SDIV, MVT::v16i16, 12+2 }, // 2*pmulhw sequence + split. in getArithmeticInstrCost()
359 { ISD::SREM, MVT::v16i16, 16+2 }, // 2*pmulhw+mul+sub sequence + split. in getArithmeticInstrCost()
362 { ISD::UDIV, MVT::v16i16, 12+2 }, // 2*pmulhuw sequence + split. in getArithmeticInstrCost()
363 { ISD::UREM, MVT::v16i16, 16+2 }, // 2*pmulhuw+mul+sub sequence + split. in getArithmeticInstrCost()
398 { ISD::SHL, MVT::v16i16, 1 }, // psllw. in getArithmeticInstrCost()
399 { ISD::SRL, MVT::v16i16, 1 }, // psrlw. in getArithmeticInstrCost()
[all …]
DX86InstrVecCompiler.td55 def : Pat<(v4i64 (bitconvert (v16i16 VR256:$src))), (v4i64 VR256:$src)>;
60 def : Pat<(v8i32 (bitconvert (v16i16 VR256:$src))), (v8i32 VR256:$src)>;
64 def : Pat<(v16i16 (bitconvert (v4i64 VR256:$src))), (v16i16 VR256:$src)>;
65 def : Pat<(v16i16 (bitconvert (v8i32 VR256:$src))), (v16i16 VR256:$src)>;
66 def : Pat<(v16i16 (bitconvert (v32i8 VR256:$src))), (v16i16 VR256:$src)>;
67 def : Pat<(v16i16 (bitconvert (v4f64 VR256:$src))), (v16i16 VR256:$src)>;
68 def : Pat<(v16i16 (bitconvert (v8f32 VR256:$src))), (v16i16 VR256:$src)>;
71 def : Pat<(v32i8 (bitconvert (v16i16 VR256:$src))), (v32i8 VR256:$src)>;
76 def : Pat<(v8f32 (bitconvert (v16i16 VR256:$src))), (v8f32 VR256:$src)>;
81 def : Pat<(v4f64 (bitconvert (v16i16 VR256:$src))), (v4f64 VR256:$src)>;
[all …]
/external/llvm/lib/Target/X86/
DX86TargetTransformInfo.cpp121 { ISD::SDIV, MVT::v16i16, 6 }, // vpmulhw sequence in getArithmeticInstrCost()
122 { ISD::UDIV, MVT::v16i16, 6 }, // vpmulhuw sequence in getArithmeticInstrCost()
165 if (ISD == ISD::SHL && LT.second == MVT::v16i16 && in getArithmeticInstrCost()
194 { ISD::SHL, MVT::v16i16, 2 }, in getArithmeticInstrCost()
195 { ISD::SRL, MVT::v16i16, 4 }, in getArithmeticInstrCost()
196 { ISD::SRA, MVT::v16i16, 4 }, in getArithmeticInstrCost()
213 { ISD::SHL, MVT::v16i16, 10 }, // extend/vpsrlvd/pack sequence. in getArithmeticInstrCost()
216 { ISD::SRL, MVT::v16i16, 10 }, // extend/vpsrlvd/pack sequence. in getArithmeticInstrCost()
219 { ISD::SRA, MVT::v16i16, 10 }, // extend/vpsravd/pack sequence. in getArithmeticInstrCost()
225 { ISD::SDIV, MVT::v16i16, 16*20 }, in getArithmeticInstrCost()
[all …]
DX86CallingConv.td62 CCIfType<[v32i8, v16i16, v8i32, v4i64, v8f32, v4f64],
145 CCIfType<[v32i8, v16i16, v8i32, v4i64, v8f32, v4f64],
340 CCIfNotVarArg<CCIfType<[v32i8, v16i16, v8i32, v4i64, v8f32, v4f64],
362 CCIfType<[v32i8, v16i16, v8i32, v4i64, v8f32, v4f64],
403 CCIfType<[v32i8, v16i16, v8i32, v4i64, v8f32, v4f64], CCPassIndirect<i64>>,
445 CCIfType<[v32i8, v16i16, v8i32, v4i64, v8f32, v4f64],
520 CCIfType<[v32i8, v16i16, v8i32, v4i64, v8f32, v4f64],
536 CCIfNotVarArg<CCIfType<[v32i8, v16i16, v8i32, v4i64, v8f32, v4f64],
555 CCIfNotVarArg<CCIfType<[v32i8, v16i16, v8i32, v4i64, v8f32, v4f64],
667 CCIfType<[v32i8, v16i16, v8i32, v4i64, v8f32, v4f64],
[all …]
/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/AArch64/
Daarch64-minmaxv.ll134 declare i16 @llvm.experimental.vector.reduce.umax.i16.v16i16(<16 x i16>)
141 %r = call i16 @llvm.experimental.vector.reduce.umax.i16.v16i16(<16 x i16> %arr.load)
158 declare i16 @llvm.experimental.vector.reduce.umin.i16.v16i16(<16 x i16>)
165 %r = call i16 @llvm.experimental.vector.reduce.umin.i16.v16i16(<16 x i16> %arr.load)
182 declare i16 @llvm.experimental.vector.reduce.smax.i16.v16i16(<16 x i16>)
189 %r = call i16 @llvm.experimental.vector.reduce.smax.i16.v16i16(<16 x i16> %arr.load)
206 declare i16 @llvm.experimental.vector.reduce.smin.i16.v16i16(<16 x i16>)
213 %r = call i16 @llvm.experimental.vector.reduce.smin.i16.v16i16(<16 x i16> %arr.load)
/external/swiftshader/third_party/LLVM/include/llvm/CodeGen/
DValueTypes.h62 v16i16 = 20, // 16 x i16 enumerator
198 case v16i16: return i16; in getVectorElementType()
220 case v16i16: return 16; in getVectorNumElements()
279 case v16i16: in getSizeInBits()
349 if (NumElements == 16) return MVT::v16i16; in getVectorVT()
505 V == MVT::v16i16 || V == MVT::v8i32 || V == MVT::v4i64); in is256BitVector()
/external/llvm/include/llvm/CodeGen/
DMachineValueType.h82 v16i16 = 34, // 16 x i16 enumerator
258 SimpleTy == MVT::v32i8 || SimpleTy == MVT::v16i16 || in is256BitVector()
338 case v16i16: in getVectorElementType()
391 case v16i16: in getVectorNumElements()
491 case v16i16: in getSizeInBits()
618 if (NumElements == 16) return MVT::v16i16; in getVectorVT()
/external/swiftshader/third_party/llvm-7.0/llvm/test/Analysis/CostModel/X86/
Dbswap.ll17 declare <16 x i16> @llvm.bswap.v16i16(<16 x i16>)
114 …an estimated cost of 14 for instruction: %bswap = call <16 x i16> @llvm.bswap.v16i16(<16 x i16> %a)
118 … an estimated cost of 2 for instruction: %bswap = call <16 x i16> @llvm.bswap.v16i16(<16 x i16> %a)
122 … an estimated cost of 4 for instruction: %bswap = call <16 x i16> @llvm.bswap.v16i16(<16 x i16> %a)
126 … an estimated cost of 1 for instruction: %bswap = call <16 x i16> @llvm.bswap.v16i16(<16 x i16> %a)
129 %bswap = call <16 x i16> @llvm.bswap.v16i16(<16 x i16> %a)
/external/swiftshader/third_party/llvm-7.0/llvm/include/llvm/Support/
DMachineValueType.h85 v16i16 = 37, // 16 x i16 enumerator
362 SimpleTy == MVT::v32i8 || SimpleTy == MVT::v16i16 || in is256BitVector()
455 case v16i16: in getVectorElementType()
544 case v16i16: in getVectorNumElements()
716 case v16i16: in getSizeInBits()
859 if (NumElements == 16) return MVT::v16i16; in getVectorVT()
/external/llvm/test/CodeGen/X86/
Davx2-cmp.ll18 define <16 x i16> @v16i16-cmp(<16 x i16> %i, <16 x i16> %j) nounwind readnone {
46 define <16 x i16> @v16i16-cmpeq(<16 x i16> %i, <16 x i16> %j) nounwind readnone {
Davx512bw-mov.ll155 …%res = call <16 x i16> @llvm.masked.load.v16i16(<16 x i16>* %addr, i32 4, <16 x i1>%mask, <16 x i1…
158 declare <16 x i16> @llvm.masked.load.v16i16(<16 x i16>*, i32, <16 x i1>, <16 x i16>)
215 call void @llvm.masked.store.v16i16(<16 x i16> %val, <16 x i16>* %addr, i32 4, <16 x i1>%mask)
218 declare void @llvm.masked.store.v16i16(<16 x i16>, <16 x i16>*, i32, <16 x i1>)
Davx-cmp.ll72 define <16 x i16> @v16i16-cmp(<16 x i16> %i, <16 x i16> %j) nounwind readnone {
116 define <16 x i16> @v16i16-cmpeq(<16 x i16> %i, <16 x i16> %j) nounwind readnone {
Dvector-popcnt-256.ll140 %out = call <16 x i16> @llvm.ctpop.v16i16(<16 x i16> %in)
203 …%out = call <16 x i16> @llvm.ctpop.v16i16(<16 x i16> <i16 256, i16 -1, i16 0, i16 255, i16 -65536,…
218 declare <16 x i16> @llvm.ctpop.v16i16(<16 x i16>)
/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/X86/
Davx512-masked_memop-16-8.ll61 …%res = call <16 x i16> @llvm.masked.load.v16i16.p0v16i16(<16 x i16>* %addr, i32 4, <16 x i1>%mask,…
64 declare <16 x i16> @llvm.masked.load.v16i16.p0v16i16(<16 x i16>*, i32, <16 x i1>, <16 x i16>)
136 …call void @llvm.masked.store.v16i16.p0v16i16(<16 x i16> %val, <16 x i16>* %addr, i32 4, <16 x i1>%…
139 declare void @llvm.masked.store.v16i16.p0v16i16(<16 x i16>, <16 x i16>*, i32, <16 x i1>)
Dbitcast-setcc-256.ll9 define i16 @v16i16(<16 x i16> %a, <16 x i16> %b) {
10 ; SSE2-SSSE3-LABEL: v16i16:
19 ; AVX1-LABEL: v16i16:
31 ; AVX2-LABEL: v16i16:
41 ; AVX512F-LABEL: v16i16:
51 ; AVX512BW-LABEL: v16i16:
Davx512bw-mov.ll148 …%res = call <16 x i16> @llvm.masked.load.v16i16(<16 x i16>* %addr, i32 4, <16 x i1>%mask, <16 x i1…
151 declare <16 x i16> @llvm.masked.load.v16i16(<16 x i16>*, i32, <16 x i1>, <16 x i16>)
205 call void @llvm.masked.store.v16i16(<16 x i16> %val, <16 x i16>* %addr, i32 4, <16 x i1>%mask)
208 declare void @llvm.masked.store.v16i16(<16 x i16>, <16 x i16>*, i32, <16 x i1>)
Dbitcast-and-setcc-256.ll168 define i16 @v16i16(<16 x i16> %a, <16 x i16> %b, <16 x i16> %c, <16 x i16> %d) {
169 ; SSE2-SSSE3-LABEL: v16i16:
182 ; AVX1-LABEL: v16i16:
200 ; AVX2-LABEL: v16i16:
214 ; AVX512F-LABEL: v16i16:
227 ; AVX512BW-LABEL: v16i16:
Dprefer-avx256-popcnt.ll82 %out = call <16 x i16> @llvm.ctpop.v16i16(<16 x i16> %in)
104 declare <16 x i16> @llvm.ctpop.v16i16(<16 x i16>)
/external/llvm/test/Analysis/CostModel/X86/
Dctbits-cost.ll17 declare <16 x i16> @llvm.ctpop.v16i16(<16 x i16>)
70 %ctpop = call <16 x i16> @llvm.ctpop.v16i16(<16 x i16> %a)
101 declare <16 x i16> @llvm.ctlz.v16i16(<16 x i16>, i1)
199 %ctlz = call <16 x i16> @llvm.ctlz.v16i16(<16 x i16> %a, i1 0)
208 %ctlz = call <16 x i16> @llvm.ctlz.v16i16(<16 x i16> %a, i1 1)
257 declare <16 x i16> @llvm.cttz.v16i16(<16 x i16>, i1)
355 %cttz = call <16 x i16> @llvm.cttz.v16i16(<16 x i16> %a, i1 0)
364 %cttz = call <16 x i16> @llvm.cttz.v16i16(<16 x i16> %a, i1 1)
Dbswap.ll16 declare <16 x i16> @llvm.bswap.v16i16(<16 x i16>)
80 %bswap = call <16 x i16> @llvm.bswap.v16i16(<16 x i16> %a)
/external/swiftshader/third_party/LLVM/lib/VMCore/
DValueTypes.cpp128 case MVT::v16i16: return "v16i16"; in getEVTString()
175 case MVT::v16i16: return VectorType::get(Type::getInt16Ty(Context), 16); in getTypeForEVT()
/external/swiftshader/third_party/LLVM/test/CodeGen/X86/
Davx-cmp.ll72 define <16 x i16> @v16i16-cmp(<16 x i16> %i, <16 x i16> %j) nounwind readnone {
116 define <16 x i16> @v16i16-cmpeq(<16 x i16> %i, <16 x i16> %j) nounwind readnone {
/external/swiftshader/third_party/LLVM/lib/Target/X86/
DX86CallingConv.td46 CCIfType<[v32i8, v16i16, v8i32, v4i64, v8f32, v4f64],
162 CCIfType<[v32i8, v16i16, v8i32, v4i64, v8f32, v4f64],
178 CCIfType<[v32i8, v16i16, v8i32, v4i64, v8f32, v4f64],
277 CCIfNotVarArg<CCIfType<[v32i8, v16i16, v8i32, v4i64, v8f32, v4f64],
285 CCIfType<[v32i8, v16i16, v8i32, v4i64, v8f32, v4f64],
/external/llvm/lib/Target/ARM/
DARMTargetTransformInfo.cpp148 { ISD::SINT_TO_FP, MVT::v16f32, MVT::v16i16, 8 }, in getCastInstrCost()
149 { ISD::UINT_TO_FP, MVT::v16f32, MVT::v16i16, 8 }, in getCastInstrCost()
175 { ISD::FP_TO_SINT, MVT::v16i16, MVT::v16f32, 8 }, in getCastInstrCost()
176 { ISD::FP_TO_UINT, MVT::v16i16, MVT::v16f32, 8 } in getCastInstrCost()

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