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Searched refs:v1i16 (Results 1 – 25 of 27) sorted by relevance

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/external/llvm/include/llvm/CodeGen/
DMachineValueType.h78 v1i16 = 30, // 1 x i16 enumerator
228 return (SimpleTy == MVT::v2i8 || SimpleTy == MVT::v1i16 || in is16BitVector()
334 case v1i16: in getVectorElementType()
420 case v1i16: in getVectorNumElements()
458 case v1i16: return 16; in getSizeInBits()
614 if (NumElements == 1) return MVT::v1i16; in getVectorVT()
DValueTypes.td55 def v1i16 : ValueType<16 , 30>; // 1 x i16 vector value
/external/clang/test/CodeGen/
Dsystemz-abi-vector.c13 typedef __attribute__((vector_size(2))) short v1i16; typedef
66 v1i16 pass_v1i16(v1i16 arg) { return arg; } in pass_v1i16()
/external/swiftshader/third_party/llvm-7.0/llvm/include/llvm/Support/
DMachineValueType.h81 v1i16 = 33, // 1 x i16 enumerator
331 return (SimpleTy == MVT::v2i8 || SimpleTy == MVT::v1i16 || in is16BitVector()
451 case v1i16: in getVectorElementType()
604 case v1i16: in getVectorNumElements()
659 case v1i16: in getSizeInBits()
855 if (NumElements == 1) return MVT::v1i16; in getVectorVT()
/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/AArch64/
Dtrunc-v1i64.ll6 ; v1i32 trunc v1i64, v1i16 trunc v1i64, v1i8 trunc v1i64.
12 ; Just like v1i16 and v1i8, there is no XTN generated.
Darm64-neon-copy.ll857 define <8 x i16> @testDUP.v1i16(<1 x i16> %a) {
858 ; CHECK-LABEL: testDUP.v1i16:
/external/llvm/test/CodeGen/AArch64/
Dtrunc-v1i64.ll6 ; v1i32 trunc v1i64, v1i16 trunc v1i64, v1i8 trunc v1i64.
12 ; Just like v1i16 and v1i8, there is no XTN generated.
Darm64-neon-copy.ll857 define <8 x i16> @testDUP.v1i16(<1 x i16> %a) {
858 ; CHECK-LABEL: testDUP.v1i16:
/external/swiftshader/third_party/llvm-7.0/llvm/lib/CodeGen/
DValueTypes.cpp159 case MVT::v1i16: return "v1i16"; in getEVTString()
240 case MVT::v1i16: return VectorType::get(Type::getInt16Ty(Context), 1); in getTypeForEVT()
/external/llvm/lib/IR/
DValueTypes.cpp162 case MVT::v1i16: return "v1i16"; in getEVTString()
240 case MVT::v1i16: return VectorType::get(Type::getInt16Ty(Context), 1); in getTypeForEVT()
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AArch64/
DAArch64SchedFalkorDetails.td682 def : InstRW<[FalkorWr_1VXVY_3cyc], (instregex "^(S|U)QADD(v1i8|v1i16|v2i16|v1i32|v1i64|v2i32|v4i…
684 def : InstRW<[FalkorWr_1VXVY_3cyc], (instregex "^(S|U)(QSHL|RSHL|QRSHL)(v1i8|v1i16|v1i32|v1i64|v2…
686 def : InstRW<[FalkorWr_1VXVY_3cyc], (instregex "^(S|U)QSUB(v1i8|v1i16|v2i16|v1i32|v1i64|v2i32|v4i…
691 def : InstRW<[FalkorWr_1VXVY_3cyc], (instregex "^(SU|US)QADD(v1i8|v1i16|v2i16|v1i32|v1i64|v2i32|v…
695 def : InstRW<[FalkorWr_1VXVY_3cyc], (instregex "^SQABS(v1i8|v1i16|v1i32|v1i64|v2i32|v4i16|v8i8)$"…
696 def : InstRW<[FalkorWr_1VXVY_3cyc], (instregex "^SQNEG(v1i8|v1i16|v1i32|v1i64)$")>;
704 … (instregex "^SQR?DMULH(v8i8|v4i16|v1i32|v2i32|v1i16)(_indexed)?$")>;
708 … (instregex "^SQRDML(A|S)H(i16|i32|v8i8|v4i16|v1i32|v2i32|v1i16)(_indexed)?$")>;
DAArch64SchedA57.td348 // D form - v1i8, v1i16, v1i32, v1i64
375 def : InstRW<[A57Write_5cyc_1W], (instregex "^(P?MUL|SQR?DMULH)(v8i8|v4i16|v2i32|v1i8|v1i16|v1i32|v…
411 def : InstRW<[A57Write_4cyc_1X], (instregex "^[SU][QR]{1,2}SHL(v1i8|v1i16|v1i32|v1i64|v8i8|v4i16|v2…
501 // D form - v1i8, v1i16, v1i32, v1i64
DAArch64SchedKryoDetails.td214 (instregex "(S|U|SU|US)QADD(v1i8|v1i16|v2i16|v1i32|v1i64)")>;
232 (instregex "(S|U)(QSHL|RSHL|QRSHL)(v1i8|v1i16|v1i32|v1i64|v8i8|v4i16|v2i32)$")>;
262 (instregex "(S|U)QSUB(v8i8|v4i16|v2i32|v1i64|v1i32|v1i16|v1i8)")>;
274 (instregex "(S|U)QXTU?N(v1i8|v1i16|v1i32)")>;
1819 (instregex "SQR?DMULH(v8i8|v4i16|v1i32|v2i32|v1i16)(_indexed)?")>;
1825 (instregex "SQ(ABS|NEG)(v1i8|v1i16|v1i32|v1i64)")>;
DAArch64SchedThunderX2T99.td1307 "(v8i8|v4i16|v2i32|v1i8|v1i16|v1i32|v1i64)" #
1336 "(v1i8|v1i16|v1i32|v1i64|v8i8|v4i16|v2i32|b|d|h|s)")>;
DAArch64InstrFormats.td6140 def v1i16 : BaseSIMDThreeScalar<U, 0b011, opc, FPR16, asm, []>;
6153 def v1i16 : BaseSIMDThreeScalar<U, 0b011, opc, FPR16, asm, []>;
6161 def v1i16: BaseSIMDThreeScalarTied<U, 0b01, R, opc, (outs FPR16:$dst),
6381 def v1i16 : BaseSIMDTwoScalar<U, {S,1}, 0b11, opc, FPR16, FPR16, asm,
6393 def v1i16 : BaseSIMDTwoScalar<U, 0b01, 0b00, opc, FPR16, FPR16, asm, []>;
6408 def v1i16 : BaseSIMDTwoScalarTied<U, 0b01, opc, FPR16, FPR16, asm, []>;
6423 def v1i16 : BaseSIMDTwoScalar<U, 0b01, 0b00, opc, FPR16, FPR32, asm, []>;
/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/ARM/
Dcttz_vector.ll11 declare <1 x i16> @llvm.cttz.v1i16(<1 x i16>, i1)
82 %tmp = call <1 x i16> @llvm.cttz.v1i16(<1 x i16> %a, i1 false)
266 %tmp = call <1 x i16> @llvm.cttz.v1i16(<1 x i16> %a, i1 true)
/external/llvm/test/CodeGen/ARM/
Dcttz_vector.ll11 declare <1 x i16> @llvm.cttz.v1i16(<1 x i16>, i1)
82 %tmp = call <1 x i16> @llvm.cttz.v1i16(<1 x i16> %a, i1 false)
266 %tmp = call <1 x i16> @llvm.cttz.v1i16(<1 x i16> %a, i1 true)
/external/llvm/lib/Target/AArch64/
DAArch64SchedA57.td344 // D form - v1i8, v1i16, v1i32, v1i64
371 def : InstRW<[A57Write_5cyc_1W], (instregex "^(P?MUL|SQR?DMULH)(v8i8|v4i16|v2i32|v1i8|v1i16|v1i32|v…
407 def : InstRW<[A57Write_4cyc_1X], (instregex "^[SU][QR]{1,2}SHL(v1i8|v1i16|v1i32|v1i64|v8i8|v4i16|v2…
497 // D form - v1i8, v1i16, v1i32, v1i64
DAArch64SchedKryoDetails.td214 (instregex "(S|U|SU|US)QADD(v1i8|v1i16|v2i16|v1i32|v1i64)")>;
232 (instregex "(S|U)(QSHL|RSHL|QRSHL)(v1i8|v1i16|v1i32|v1i64|v8i8|v4i16|v2i32)$")>;
262 (instregex "(S|U)QSUB(v8i8|v4i16|v2i32|v1i64|v1i32|v1i16|v1i8)")>;
274 (instregex "(S|U)QXTU?N(v1i8|v1i16|v1i32)")>;
1799 (instregex "SQR?DMULH(v8i8|v4i16|v1i32|v2i32|v1i16)(_indexed)?")>;
1805 (instregex "SQ(ABS|NEG)(v1i8|v1i16|v1i32|v1i64)")>;
DAArch64InstrFormats.td5688 def v1i16 : BaseSIMDThreeScalar<U, 0b011, opc, FPR16, asm, []>;
5701 def v1i16 : BaseSIMDThreeScalar<U, 0b011, opc, FPR16, asm, []>;
5709 def v1i16: BaseSIMDThreeScalarTied<U, 0b01, R, opc, (outs FPR16:$dst),
5929 def v1i16 : BaseSIMDTwoScalar<U, {S,1}, 0b11, opc, FPR16, FPR16, asm,
5941 def v1i16 : BaseSIMDTwoScalar<U, 0b01, 0b00, opc, FPR16, FPR16, asm, []>;
5956 def v1i16 : BaseSIMDTwoScalarTied<U, 0b01, opc, FPR16, FPR16, asm, []>;
5971 def v1i16 : BaseSIMDTwoScalar<U, 0b01, 0b00, opc, FPR16, FPR32, asm, []>;
/external/swiftshader/third_party/llvm-7.0/llvm/include/llvm/CodeGen/
DValueTypes.td57 def v1i16 : ValueType<16 , 33>; // 1 x i16 vector value
/external/llvm/utils/TableGen/
DCodeGenTarget.cpp90 case MVT::v1i16: return "MVT::v1i16"; in getEnumName()
/external/swiftshader/third_party/llvm-7.0/llvm/utils/TableGen/
DCodeGenTarget.cpp98 case MVT::v1i16: return "MVT::v1i16"; in getEnumName()
/external/llvm/include/llvm/IR/
DIntrinsics.td188 def llvm_v1i16_ty : LLVMType<v1i16>; // 1 x i16
/external/swiftshader/third_party/llvm-7.0/llvm/include/llvm/IR/
DIntrinsics.td216 def llvm_v1i16_ty : LLVMType<v1i16>; // 1 x i16

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