1//=- AArch64SchedA57.td - ARM Cortex-A57 Scheduling Defs -----*- tablegen -*-=// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file defines the machine model for ARM Cortex-A57 to support 11// instruction scheduling and other instruction cost heuristics. 12// 13//===----------------------------------------------------------------------===// 14 15//===----------------------------------------------------------------------===// 16// The Cortex-A57 is a traditional superscaler microprocessor with a 17// conservative 3-wide in-order stage for decode and dispatch. Combined with the 18// much wider out-of-order issue stage, this produced a need to carefully 19// schedule micro-ops so that all three decoded each cycle are successfully 20// issued as the reservation station(s) simply don't stay occupied for long. 21// Therefore, IssueWidth is set to the narrower of the two at three, while still 22// modeling the machine as out-of-order. 23 24def CortexA57Model : SchedMachineModel { 25 let IssueWidth = 3; // 3-way decode and dispatch 26 let MicroOpBufferSize = 128; // 128 micro-op re-order buffer 27 let LoadLatency = 4; // Optimistic load latency 28 let MispredictPenalty = 14; // Fetch + Decode/Rename/Dispatch + Branch 29 30 // Enable partial & runtime unrolling. The magic number is chosen based on 31 // experiments and benchmarking data. 32 let LoopMicroOpBufferSize = 16; 33 let CompleteModel = 1; 34} 35 36//===----------------------------------------------------------------------===// 37// Define each kind of processor resource and number available on Cortex-A57. 38// Cortex A-57 has 8 pipelines that each has its own 8-entry queue where 39// micro-ops wait for their operands and then issue out-of-order. 40 41def A57UnitB : ProcResource<1>; // Type B micro-ops 42def A57UnitI : ProcResource<2>; // Type I micro-ops 43def A57UnitM : ProcResource<1>; // Type M micro-ops 44def A57UnitL : ProcResource<1>; // Type L micro-ops 45def A57UnitS : ProcResource<1>; // Type S micro-ops 46def A57UnitX : ProcResource<1>; // Type X micro-ops 47def A57UnitW : ProcResource<1>; // Type W micro-ops 48let SchedModel = CortexA57Model in { 49 def A57UnitV : ProcResGroup<[A57UnitX, A57UnitW]>; // Type V micro-ops 50} 51 52let SchedModel = CortexA57Model in { 53 54//===----------------------------------------------------------------------===// 55// Define customized scheduler read/write types specific to the Cortex-A57. 56 57include "AArch64SchedA57WriteRes.td" 58 59//===----------------------------------------------------------------------===// 60// Map the target-defined scheduler read/write resources and latency for 61// Cortex-A57. The Cortex-A57 types are directly associated with resources, so 62// defining the aliases precludes the need for mapping them using WriteRes. The 63// aliases are sufficient for creating a coarse, working model. As the model 64// evolves, InstRWs will be used to override some of these SchedAliases. 65// 66// WARNING: Using SchedAliases is convenient and works well for latency and 67// resource lookup for instructions. However, this creates an entry in 68// AArch64WriteLatencyTable with a WriteResourceID of 0, breaking 69// any SchedReadAdvance since the lookup will fail. 70 71def : SchedAlias<WriteImm, A57Write_1cyc_1I>; 72def : SchedAlias<WriteI, A57Write_1cyc_1I>; 73def : SchedAlias<WriteISReg, A57Write_2cyc_1M>; 74def : SchedAlias<WriteIEReg, A57Write_2cyc_1M>; 75def : SchedAlias<WriteExtr, A57Write_1cyc_1I>; 76def : SchedAlias<WriteIS, A57Write_1cyc_1I>; 77def : SchedAlias<WriteID32, A57Write_19cyc_1M>; 78def : SchedAlias<WriteID64, A57Write_35cyc_1M>; 79def : WriteRes<WriteIM32, [A57UnitM]> { let Latency = 3; } 80def : WriteRes<WriteIM64, [A57UnitM]> { let Latency = 5; } 81def : SchedAlias<WriteBr, A57Write_1cyc_1B>; 82def : SchedAlias<WriteBrReg, A57Write_1cyc_1B>; 83def : SchedAlias<WriteLD, A57Write_4cyc_1L>; 84def : SchedAlias<WriteST, A57Write_1cyc_1S>; 85def : SchedAlias<WriteSTP, A57Write_1cyc_1S>; 86def : SchedAlias<WriteAdr, A57Write_1cyc_1I>; 87def : SchedAlias<WriteLDIdx, A57Write_4cyc_1I_1L>; 88def : SchedAlias<WriteSTIdx, A57Write_1cyc_1I_1S>; 89def : SchedAlias<WriteF, A57Write_3cyc_1V>; 90def : SchedAlias<WriteFCmp, A57Write_3cyc_1V>; 91def : SchedAlias<WriteFCvt, A57Write_5cyc_1V>; 92def : SchedAlias<WriteFCopy, A57Write_5cyc_1L>; 93def : SchedAlias<WriteFImm, A57Write_3cyc_1V>; 94def : SchedAlias<WriteFMul, A57Write_5cyc_1V>; 95def : SchedAlias<WriteFDiv, A57Write_18cyc_1X>; 96def : SchedAlias<WriteV, A57Write_3cyc_1V>; 97def : SchedAlias<WriteVLD, A57Write_5cyc_1L>; 98def : SchedAlias<WriteVST, A57Write_1cyc_1S>; 99 100def : WriteRes<WriteAtomic, []> { let Unsupported = 1; } 101 102def : WriteRes<WriteSys, []> { let Latency = 1; } 103def : WriteRes<WriteBarrier, []> { let Latency = 1; } 104def : WriteRes<WriteHint, []> { let Latency = 1; } 105 106def : WriteRes<WriteLDHi, []> { let Latency = 4; } 107 108// Forwarding logic is only modeled for multiply and accumulate 109def : ReadAdvance<ReadI, 0>; 110def : ReadAdvance<ReadISReg, 0>; 111def : ReadAdvance<ReadIEReg, 0>; 112def : ReadAdvance<ReadIM, 0>; 113def : ReadAdvance<ReadIMA, 2, [WriteIM32, WriteIM64]>; 114def : ReadAdvance<ReadID, 0>; 115def : ReadAdvance<ReadExtrHi, 0>; 116def : ReadAdvance<ReadAdrBase, 0>; 117def : ReadAdvance<ReadVLD, 0>; 118 119 120//===----------------------------------------------------------------------===// 121// Specialize the coarse model by associating instruction groups with the 122// subtarget-defined types. As the modeled is refined, this will override most 123// of the above ShchedAlias mappings. 124 125// Miscellaneous 126// ----------------------------------------------------------------------------- 127 128def : InstRW<[WriteI], (instrs COPY)>; 129 130 131// Branch Instructions 132// ----------------------------------------------------------------------------- 133 134def : InstRW<[A57Write_1cyc_1B_1I], (instrs BL)>; 135def : InstRW<[A57Write_2cyc_1B_1I], (instrs BLR)>; 136 137 138// Shifted Register with Shift == 0 139// ---------------------------------------------------------------------------- 140 141def A57WriteISReg : SchedWriteVariant<[ 142 SchedVar<RegShiftedPred, [WriteISReg]>, 143 SchedVar<NoSchedPred, [WriteI]>]>; 144def : InstRW<[A57WriteISReg], (instregex ".*rs$")>; 145 146 147// Divide and Multiply Instructions 148// ----------------------------------------------------------------------------- 149 150// Multiply high 151def : InstRW<[A57Write_6cyc_1M], (instrs SMULHrr, UMULHrr)>; 152 153 154// Miscellaneous Data-Processing Instructions 155// ----------------------------------------------------------------------------- 156 157def : InstRW<[A57Write_1cyc_1I], (instrs EXTRWrri)>; 158def : InstRW<[A57Write_3cyc_1I_1M], (instrs EXTRXrri)>; 159def : InstRW<[A57Write_2cyc_1M], (instregex "BFM")>; 160 161 162// Cryptography Extensions 163// ----------------------------------------------------------------------------- 164 165def : InstRW<[A57Write_3cyc_1W], (instregex "^AES")>; 166def : InstRW<[A57Write_6cyc_2V], (instregex "^SHA1SU0")>; 167def : InstRW<[A57Write_3cyc_1W], (instregex "^SHA1(H|SU1)")>; 168def : InstRW<[A57Write_6cyc_2W], (instregex "^SHA1[CMP]")>; 169def : InstRW<[A57Write_3cyc_1W], (instregex "^SHA256SU0")>; 170def : InstRW<[A57Write_6cyc_2W], (instregex "^SHA256(H|H2|SU1)")>; 171def : InstRW<[A57Write_3cyc_1W], (instregex "^CRC32")>; 172 173 174// Vector Load 175// ----------------------------------------------------------------------------- 176 177def : InstRW<[A57Write_8cyc_1L_1V], (instregex "LD1i(8|16|32)$")>; 178def : InstRW<[A57Write_8cyc_1L_1V, WriteAdr], (instregex "LD1i(8|16|32)_POST$")>; 179def : InstRW<[A57Write_5cyc_1L], (instregex "LD1i(64)$")>; 180def : InstRW<[A57Write_5cyc_1L, WriteAdr], (instregex "LD1i(64)_POST$")>; 181 182def : InstRW<[A57Write_8cyc_1L_1V], (instregex "LD1Rv(8b|4h|2s)$")>; 183def : InstRW<[A57Write_8cyc_1L_1V, WriteAdr], (instregex "LD1Rv(8b|4h|2s)_POST$")>; 184def : InstRW<[A57Write_5cyc_1L], (instregex "LD1Rv(1d)$")>; 185def : InstRW<[A57Write_5cyc_1L, WriteAdr], (instregex "LD1Rv(1d)_POST$")>; 186def : InstRW<[A57Write_8cyc_1L_1V], (instregex "LD1Rv(16b|8h|4s|2d)$")>; 187def : InstRW<[A57Write_8cyc_1L_1V, WriteAdr], (instregex "LD1Rv(16b|8h|4s|2d)_POST$")>; 188 189def : InstRW<[A57Write_5cyc_1L], (instregex "LD1Onev(8b|4h|2s|1d)$")>; 190def : InstRW<[A57Write_5cyc_1L, WriteAdr], (instregex "LD1Onev(8b|4h|2s|1d)_POST$")>; 191def : InstRW<[A57Write_5cyc_1L], (instregex "LD1Onev(16b|8h|4s|2d)$")>; 192def : InstRW<[A57Write_5cyc_1L, WriteAdr], (instregex "LD1Onev(16b|8h|4s|2d)_POST$")>; 193def : InstRW<[A57Write_5cyc_1L], (instregex "LD1Twov(8b|4h|2s|1d)$")>; 194def : InstRW<[A57Write_5cyc_1L, WriteAdr], (instregex "LD1Twov(8b|4h|2s|1d)_POST$")>; 195def : InstRW<[A57Write_6cyc_2L], (instregex "LD1Twov(16b|8h|4s|2d)$")>; 196def : InstRW<[A57Write_6cyc_2L, WriteAdr], (instregex "LD1Twov(16b|8h|4s|2d)_POST$")>; 197def : InstRW<[A57Write_6cyc_2L], (instregex "LD1Threev(8b|4h|2s|1d)$")>; 198def : InstRW<[A57Write_6cyc_2L, WriteAdr], (instregex "LD1Threev(8b|4h|2s|1d)_POST$")>; 199def : InstRW<[A57Write_7cyc_3L], (instregex "LD1Threev(16b|8h|4s|2d)$")>; 200def : InstRW<[A57Write_7cyc_3L, WriteAdr], (instregex "LD1Threev(16b|8h|4s|2d)_POST$")>; 201def : InstRW<[A57Write_6cyc_2L], (instregex "LD1Fourv(8b|4h|2s|1d)$")>; 202def : InstRW<[A57Write_6cyc_2L, WriteAdr], (instregex "LD1Fourv(8b|4h|2s|1d)_POST$")>; 203def : InstRW<[A57Write_8cyc_4L], (instregex "LD1Fourv(16b|8h|4s|2d)$")>; 204def : InstRW<[A57Write_8cyc_4L, WriteAdr], (instregex "LD1Fourv(16b|8h|4s|2d)_POST$")>; 205 206def : InstRW<[A57Write_8cyc_1L_2V], (instregex "LD2i(8|16)$")>; 207def : InstRW<[A57Write_8cyc_1L_2V, WriteAdr], (instregex "LD2i(8|16)_POST$")>; 208def : InstRW<[A57Write_6cyc_2L], (instregex "LD2i(32)$")>; 209def : InstRW<[A57Write_6cyc_2L, WriteAdr], (instregex "LD2i(32)_POST$")>; 210def : InstRW<[A57Write_8cyc_1L_1V], (instregex "LD2i(64)$")>; 211def : InstRW<[A57Write_8cyc_1L_1V, WriteAdr], (instregex "LD2i(64)_POST$")>; 212 213def : InstRW<[A57Write_8cyc_1L_1V], (instregex "LD2Rv(8b|4h|2s)$")>; 214def : InstRW<[A57Write_8cyc_1L_1V, WriteAdr], (instregex "LD2Rv(8b|4h|2s)_POST$")>; 215def : InstRW<[A57Write_5cyc_1L], (instregex "LD2Rv(1d)$")>; 216def : InstRW<[A57Write_5cyc_1L, WriteAdr], (instregex "LD2Rv(1d)_POST$")>; 217def : InstRW<[A57Write_8cyc_1L_2V], (instregex "LD2Rv(16b|8h|4s|2d)$")>; 218def : InstRW<[A57Write_8cyc_1L_2V, WriteAdr], (instregex "LD2Rv(16b|8h|4s|2d)_POST$")>; 219 220def : InstRW<[A57Write_8cyc_1L_1V], (instregex "LD2Twov(8b|4h|2s)$")>; 221def : InstRW<[A57Write_8cyc_1L_1V, WriteAdr], (instregex "LD2Twov(8b|4h|2s)_POST$")>; 222def : InstRW<[A57Write_9cyc_2L_2V], (instregex "LD2Twov(16b|8h|4s)$")>; 223def : InstRW<[A57Write_9cyc_2L_2V, WriteAdr], (instregex "LD2Twov(16b|8h|4s)_POST$")>; 224def : InstRW<[A57Write_6cyc_2L], (instregex "LD2Twov(2d)$")>; 225def : InstRW<[A57Write_6cyc_2L, WriteAdr], (instregex "LD2Twov(2d)_POST$")>; 226 227def : InstRW<[A57Write_9cyc_1L_3V], (instregex "LD3i(8|16)$")>; 228def : InstRW<[A57Write_9cyc_1L_3V, WriteAdr], (instregex "LD3i(8|16)_POST$")>; 229def : InstRW<[A57Write_8cyc_1L_2V], (instregex "LD3i(32)$")>; 230def : InstRW<[A57Write_8cyc_1L_2V, WriteAdr], (instregex "LD3i(32)_POST$")>; 231def : InstRW<[A57Write_6cyc_2L], (instregex "LD3i(64)$")>; 232def : InstRW<[A57Write_6cyc_2L, WriteAdr], (instregex "LD3i(64)_POST$")>; 233 234def : InstRW<[A57Write_8cyc_1L_2V], (instregex "LD3Rv(8b|4h|2s)$")>; 235def : InstRW<[A57Write_8cyc_1L_2V, WriteAdr], (instregex "LD3Rv(8b|4h|2s)_POST$")>; 236def : InstRW<[A57Write_6cyc_2L], (instregex "LD3Rv(1d)$")>; 237def : InstRW<[A57Write_6cyc_2L, WriteAdr], (instregex "LD3Rv(1d)_POST$")>; 238def : InstRW<[A57Write_9cyc_1L_3V], (instregex "LD3Rv(16b|8h|4s)$")>; 239def : InstRW<[A57Write_9cyc_1L_3V, WriteAdr], (instregex "LD3Rv(16b|8h|4s)_POST$")>; 240def : InstRW<[A57Write_9cyc_2L_3V], (instregex "LD3Rv(2d)$")>; 241def : InstRW<[A57Write_9cyc_2L_3V, WriteAdr], (instregex "LD3Rv(2d)_POST$")>; 242 243def : InstRW<[A57Write_9cyc_2L_2V], (instregex "LD3Threev(8b|4h|2s)$")>; 244def : InstRW<[A57Write_9cyc_2L_2V, WriteAdr], (instregex "LD3Threev(8b|4h|2s)_POST$")>; 245def : InstRW<[A57Write_10cyc_3L_4V], (instregex "LD3Threev(16b|8h|4s)$")>; 246def : InstRW<[A57Write_10cyc_3L_4V, WriteAdr], (instregex "LD3Threev(16b|8h|4s)_POST$")>; 247def : InstRW<[A57Write_8cyc_4L], (instregex "LD3Threev(2d)$")>; 248def : InstRW<[A57Write_8cyc_4L, WriteAdr], (instregex "LD3Threev(2d)_POST$")>; 249 250def : InstRW<[A57Write_9cyc_2L_3V], (instregex "LD4i(8|16)$")>; 251def : InstRW<[A57Write_9cyc_2L_3V, WriteAdr], (instregex "LD4i(8|16)_POST$")>; 252def : InstRW<[A57Write_8cyc_1L_2V], (instregex "LD4i(32)$")>; 253def : InstRW<[A57Write_8cyc_1L_2V, WriteAdr], (instregex "LD4i(32)_POST$")>; 254def : InstRW<[A57Write_9cyc_2L_3V], (instregex "LD4i(64)$")>; 255def : InstRW<[A57Write_9cyc_2L_3V, WriteAdr], (instregex "LD4i(64)_POST$")>; 256 257def : InstRW<[A57Write_8cyc_1L_2V], (instregex "LD4Rv(8b|4h|2s)$")>; 258def : InstRW<[A57Write_8cyc_1L_2V, WriteAdr], (instregex "LD4Rv(8b|4h|2s)_POST$")>; 259def : InstRW<[A57Write_6cyc_2L], (instregex "LD4Rv(1d)$")>; 260def : InstRW<[A57Write_6cyc_2L, WriteAdr], (instregex "LD4Rv(1d)_POST$")>; 261def : InstRW<[A57Write_9cyc_2L_3V], (instregex "LD4Rv(16b|8h|4s)$")>; 262def : InstRW<[A57Write_9cyc_2L_3V, WriteAdr], (instregex "LD4Rv(16b|8h|4s)_POST$")>; 263def : InstRW<[A57Write_9cyc_2L_4V], (instregex "LD4Rv(2d)$")>; 264def : InstRW<[A57Write_9cyc_2L_4V, WriteAdr], (instregex "LD4Rv(2d)_POST$")>; 265 266def : InstRW<[A57Write_9cyc_2L_2V], (instregex "LD4Fourv(8b|4h|2s)$")>; 267def : InstRW<[A57Write_9cyc_2L_2V, WriteAdr], (instregex "LD4Fourv(8b|4h|2s)_POST$")>; 268def : InstRW<[A57Write_11cyc_4L_4V], (instregex "LD4Fourv(16b|8h|4s)$")>; 269def : InstRW<[A57Write_11cyc_4L_4V, WriteAdr], (instregex "LD4Fourv(16b|8h|4s)_POST$")>; 270def : InstRW<[A57Write_8cyc_4L], (instregex "LD4Fourv(2d)$")>; 271def : InstRW<[A57Write_8cyc_4L, WriteAdr], (instregex "LD4Fourv(2d)_POST$")>; 272 273// Vector Store 274// ----------------------------------------------------------------------------- 275 276def : InstRW<[A57Write_1cyc_1S], (instregex "ST1i(8|16|32)$")>; 277def : InstRW<[A57Write_1cyc_1S, WriteAdr], (instregex "ST1i(8|16|32)_POST$")>; 278def : InstRW<[A57Write_3cyc_1S_1V], (instregex "ST1i(64)$")>; 279def : InstRW<[A57Write_3cyc_1S_1V, WriteAdr], (instregex "ST1i(64)_POST$")>; 280 281def : InstRW<[A57Write_1cyc_1S], (instregex "ST1Onev(8b|4h|2s|1d)$")>; 282def : InstRW<[A57Write_1cyc_1S, WriteAdr], (instregex "ST1Onev(8b|4h|2s|1d)_POST$")>; 283def : InstRW<[A57Write_2cyc_2S], (instregex "ST1Onev(16b|8h|4s|2d)$")>; 284def : InstRW<[A57Write_2cyc_2S, WriteAdr], (instregex "ST1Onev(16b|8h|4s|2d)_POST$")>; 285def : InstRW<[A57Write_2cyc_2S], (instregex "ST1Twov(8b|4h|2s|1d)$")>; 286def : InstRW<[A57Write_2cyc_2S, WriteAdr], (instregex "ST1Twov(8b|4h|2s|1d)_POST$")>; 287def : InstRW<[A57Write_4cyc_4S], (instregex "ST1Twov(16b|8h|4s|2d)$")>; 288def : InstRW<[A57Write_4cyc_4S, WriteAdr], (instregex "ST1Twov(16b|8h|4s|2d)_POST$")>; 289def : InstRW<[A57Write_3cyc_3S], (instregex "ST1Threev(8b|4h|2s|1d)$")>; 290def : InstRW<[A57Write_3cyc_3S, WriteAdr], (instregex "ST1Threev(8b|4h|2s|1d)_POST$")>; 291def : InstRW<[A57Write_6cyc_6S], (instregex "ST1Threev(16b|8h|4s|2d)$")>; 292def : InstRW<[A57Write_6cyc_6S, WriteAdr], (instregex "ST1Threev(16b|8h|4s|2d)_POST$")>; 293def : InstRW<[A57Write_4cyc_4S], (instregex "ST1Fourv(8b|4h|2s|1d)$")>; 294def : InstRW<[A57Write_4cyc_4S, WriteAdr], (instregex "ST1Fourv(8b|4h|2s|1d)_POST$")>; 295def : InstRW<[A57Write_8cyc_8S], (instregex "ST1Fourv(16b|8h|4s|2d)$")>; 296def : InstRW<[A57Write_8cyc_8S, WriteAdr], (instregex "ST1Fourv(16b|8h|4s|2d)_POST$")>; 297 298def : InstRW<[A57Write_3cyc_1S_1V], (instregex "ST2i(8|16|32)$")>; 299def : InstRW<[A57Write_3cyc_1S_1V, WriteAdr], (instregex "ST2i(8|16|32)_POST$")>; 300def : InstRW<[A57Write_2cyc_2S], (instregex "ST2i(64)$")>; 301def : InstRW<[A57Write_2cyc_2S, WriteAdr], (instregex "ST2i(64)_POST$")>; 302 303def : InstRW<[A57Write_3cyc_2S_1V], (instregex "ST2Twov(8b|4h|2s)$")>; 304def : InstRW<[A57Write_3cyc_2S_1V, WriteAdr], (instregex "ST2Twov(8b|4h|2s)_POST$")>; 305def : InstRW<[A57Write_4cyc_4S_2V], (instregex "ST2Twov(16b|8h|4s)$")>; 306def : InstRW<[A57Write_4cyc_4S_2V, WriteAdr], (instregex "ST2Twov(16b|8h|4s)_POST$")>; 307def : InstRW<[A57Write_4cyc_4S], (instregex "ST2Twov(2d)$")>; 308def : InstRW<[A57Write_4cyc_4S, WriteAdr], (instregex "ST2Twov(2d)_POST$")>; 309 310def : InstRW<[A57Write_3cyc_1S_1V], (instregex "ST3i(8|16)$")>; 311def : InstRW<[A57Write_3cyc_1S_1V, WriteAdr], (instregex "ST3i(8|16)_POST$")>; 312def : InstRW<[A57Write_3cyc_3S], (instregex "ST3i(32)$")>; 313def : InstRW<[A57Write_3cyc_3S, WriteAdr], (instregex "ST3i(32)_POST$")>; 314def : InstRW<[A57Write_3cyc_2S_1V], (instregex "ST3i(64)$")>; 315def : InstRW<[A57Write_3cyc_2S_1V, WriteAdr], (instregex "ST3i(64)_POST$")>; 316 317def : InstRW<[A57Write_3cyc_3S_2V], (instregex "ST3Threev(8b|4h|2s)$")>; 318def : InstRW<[A57Write_3cyc_3S_2V, WriteAdr], (instregex "ST3Threev(8b|4h|2s)_POST$")>; 319def : InstRW<[A57Write_6cyc_6S_4V], (instregex "ST3Threev(16b|8h|4s)$")>; 320def : InstRW<[A57Write_6cyc_6S_4V, WriteAdr], (instregex "ST3Threev(16b|8h|4s)_POST$")>; 321def : InstRW<[A57Write_6cyc_6S], (instregex "ST3Threev(2d)$")>; 322def : InstRW<[A57Write_6cyc_6S, WriteAdr], (instregex "ST3Threev(2d)_POST$")>; 323 324def : InstRW<[A57Write_3cyc_1S_1V], (instregex "ST4i(8|16)$")>; 325def : InstRW<[A57Write_3cyc_1S_1V, WriteAdr], (instregex "ST4i(8|16)_POST$")>; 326def : InstRW<[A57Write_4cyc_4S], (instregex "ST4i(32)$")>; 327def : InstRW<[A57Write_4cyc_4S, WriteAdr], (instregex "ST4i(32)_POST$")>; 328def : InstRW<[A57Write_3cyc_2S_1V], (instregex "ST4i(64)$")>; 329def : InstRW<[A57Write_3cyc_2S_1V, WriteAdr], (instregex "ST4i(64)_POST$")>; 330 331def : InstRW<[A57Write_4cyc_4S_2V], (instregex "ST4Fourv(8b|4h|2s)$")>; 332def : InstRW<[A57Write_4cyc_4S_2V, WriteAdr], (instregex "ST4Fourv(8b|4h|2s)_POST$")>; 333def : InstRW<[A57Write_8cyc_8S_4V], (instregex "ST4Fourv(16b|8h|4s)$")>; 334def : InstRW<[A57Write_8cyc_8S_4V, WriteAdr], (instregex "ST4Fourv(16b|8h|4s)_POST$")>; 335def : InstRW<[A57Write_8cyc_8S], (instregex "ST4Fourv(2d)$")>; 336def : InstRW<[A57Write_8cyc_8S, WriteAdr], (instregex "ST4Fourv(2d)_POST$")>; 337 338// Vector - Integer 339// ----------------------------------------------------------------------------- 340 341// Reference for forms in this group 342// D form - v8i8, v4i16, v2i32 343// Q form - v16i8, v8i16, v4i32 344// D form - v1i8, v1i16, v1i32, v1i64 345// Q form - v16i8, v8i16, v4i32, v2i64 346// D form - v8i8_v8i16, v4i16_v4i32, v2i32_v2i64 347// Q form - v16i8_v8i16, v8i16_v4i32, v4i32_v2i64 348 349// ASIMD absolute diff accum, D-form 350def : InstRW<[A57Write_4cyc_1X], (instregex "^[SU]ABA(v8i8|v4i16|v2i32)$")>; 351// ASIMD absolute diff accum, Q-form 352def : InstRW<[A57Write_5cyc_2X], (instregex "^[SU]ABA(v16i8|v8i16|v4i32)$")>; 353// ASIMD absolute diff accum long 354def : InstRW<[A57Write_4cyc_1X], (instregex "^[SU]ABAL")>; 355 356// ASIMD arith, reduce, 4H/4S 357def : InstRW<[A57Write_4cyc_1X], (instregex "^[SU]?ADDL?V(v8i8|v4i16|v2i32)v$")>; 358// ASIMD arith, reduce, 8B/8H 359def : InstRW<[A57Write_7cyc_1V_1X], (instregex "^[SU]?ADDL?V(v8i16|v4i32)v$")>; 360// ASIMD arith, reduce, 16B 361def : InstRW<[A57Write_8cyc_2X], (instregex "^[SU]?ADDL?Vv16i8v$")>; 362 363// ASIMD max/min, reduce, 4H/4S 364def : InstRW<[A57Write_4cyc_1X], (instregex "^[SU](MIN|MAX)V(v4i16|v4i32)v$")>; 365// ASIMD max/min, reduce, 8B/8H 366def : InstRW<[A57Write_7cyc_1V_1X], (instregex "^[SU](MIN|MAX)V(v8i8|v8i16)v$")>; 367// ASIMD max/min, reduce, 16B 368def : InstRW<[A57Write_8cyc_2X], (instregex "^[SU](MIN|MAX)Vv16i8v$")>; 369 370// ASIMD multiply, D-form 371def : InstRW<[A57Write_5cyc_1W], (instregex "^(P?MUL|SQR?DMULH)(v8i8|v4i16|v2i32|v1i8|v1i16|v1i32|v1i64)(_indexed)?$")>; 372// ASIMD multiply, Q-form 373def : InstRW<[A57Write_6cyc_2W], (instregex "^(P?MUL|SQR?DMULH)(v16i8|v8i16|v4i32)(_indexed)?$")>; 374 375// ASIMD multiply accumulate, D-form 376def : InstRW<[A57Write_5cyc_1W], (instregex "^ML[AS](v8i8|v4i16|v2i32)(_indexed)?$")>; 377// ASIMD multiply accumulate, Q-form 378def : InstRW<[A57Write_6cyc_2W], (instregex "^ML[AS](v16i8|v8i16|v4i32)(_indexed)?$")>; 379 380// ASIMD multiply accumulate long 381// ASIMD multiply accumulate saturating long 382def A57WriteIVMA : SchedWriteRes<[A57UnitW]> { let Latency = 5; } 383def A57ReadIVMA4 : SchedReadAdvance<4, [A57WriteIVMA]>; 384def : InstRW<[A57WriteIVMA, A57ReadIVMA4], (instregex "^(S|U|SQD)ML[AS]L")>; 385 386// ASIMD multiply long 387def : InstRW<[A57Write_5cyc_1W], (instregex "^(S|U|SQD)MULL")>; 388def : InstRW<[A57Write_5cyc_1W], (instregex "^PMULL(v8i8|v16i8)")>; 389def : InstRW<[A57Write_3cyc_1W], (instregex "^PMULL(v1i64|v2i64)")>; 390 391// ASIMD pairwise add and accumulate 392// ASIMD shift accumulate 393def A57WriteIVA : SchedWriteRes<[A57UnitX]> { let Latency = 4; } 394def A57ReadIVA3 : SchedReadAdvance<3, [A57WriteIVA]>; 395def : InstRW<[A57WriteIVA, A57ReadIVA3], (instregex "^[SU]ADALP")>; 396def : InstRW<[A57WriteIVA, A57ReadIVA3], (instregex "^(S|SR|U|UR)SRA")>; 397 398// ASIMD shift by immed, complex 399def : InstRW<[A57Write_4cyc_1X], (instregex "^[SU]?(Q|R){1,2}SHR")>; 400def : InstRW<[A57Write_4cyc_1X], (instregex "^SQSHLU")>; 401 402 403// ASIMD shift by register, basic, Q-form 404def : InstRW<[A57Write_4cyc_2X], (instregex "^[SU]SHL(v16i8|v8i16|v4i32|v2i64)")>; 405 406// ASIMD shift by register, complex, D-form 407def : InstRW<[A57Write_4cyc_1X], (instregex "^[SU][QR]{1,2}SHL(v1i8|v1i16|v1i32|v1i64|v8i8|v4i16|v2i32|b|d|h|s)")>; 408 409// ASIMD shift by register, complex, Q-form 410def : InstRW<[A57Write_5cyc_2X], (instregex "^[SU][QR]{1,2}SHL(v16i8|v8i16|v4i32|v2i64)")>; 411 412 413// Vector - Floating Point 414// ----------------------------------------------------------------------------- 415 416// Reference for forms in this group 417// D form - v2f32 418// Q form - v4f32, v2f64 419// D form - 32, 64 420// D form - v1i32, v1i64 421// D form - v2i32 422// Q form - v4i32, v2i64 423 424// ASIMD FP arith, normal, D-form 425def : InstRW<[A57Write_5cyc_1V], (instregex "^(FABD|FADD|FSUB)(v2f32|32|64|v2i32p)")>; 426// ASIMD FP arith, normal, Q-form 427def : InstRW<[A57Write_5cyc_2V], (instregex "^(FABD|FADD|FSUB)(v4f32|v2f64|v2i64p)")>; 428 429// ASIMD FP arith, pairwise, D-form 430def : InstRW<[A57Write_5cyc_1V], (instregex "^FADDP(v2f32|32|64|v2i32)")>; 431// ASIMD FP arith, pairwise, Q-form 432def : InstRW<[A57Write_9cyc_3V], (instregex "^FADDP(v4f32|v2f64|v2i64)")>; 433 434// ASIMD FP compare, D-form 435def : InstRW<[A57Write_5cyc_1V], (instregex "^(FACGE|FACGT|FCMEQ|FCMGE|FCMGT|FCMLE|FCMLT)(v2f32|32|64|v1i32|v2i32|v1i64)")>; 436// ASIMD FP compare, Q-form 437def : InstRW<[A57Write_5cyc_2V], (instregex "^(FACGE|FACGT|FCMEQ|FCMGE|FCMGT|FCMLE|FCMLT)(v4f32|v2f64|v4i32|v2i64)")>; 438 439// ASIMD FP convert, long and narrow 440def : InstRW<[A57Write_8cyc_3V], (instregex "^FCVT(L|N|XN)v")>; 441// ASIMD FP convert, other, D-form 442def : InstRW<[A57Write_5cyc_1V], (instregex "^[FVSU]CVT([AMNPZ][SU])?(_Int)?(v2f32|v1i32|v2i32|v1i64)")>; 443// ASIMD FP convert, other, Q-form 444def : InstRW<[A57Write_5cyc_2V], (instregex "^[FVSU]CVT([AMNPZ][SU])?(_Int)?(v4f32|v2f64|v4i32|v2i64)")>; 445 446// ASIMD FP divide, D-form, F32 447def : InstRW<[A57Write_18cyc_1X], (instregex "FDIVv2f32")>; 448// ASIMD FP divide, Q-form, F32 449def : InstRW<[A57Write_36cyc_2X], (instregex "FDIVv4f32")>; 450// ASIMD FP divide, Q-form, F64 451def : InstRW<[A57Write_64cyc_2X], (instregex "FDIVv2f64")>; 452 453// Note: These were simply duplicated from ASIMD FDIV because of missing documentation 454// ASIMD FP square root, D-form, F32 455def : InstRW<[A57Write_18cyc_1X], (instregex "FSQRTv2f32")>; 456// ASIMD FP square root, Q-form, F32 457def : InstRW<[A57Write_36cyc_2X], (instregex "FSQRTv4f32")>; 458// ASIMD FP square root, Q-form, F64 459def : InstRW<[A57Write_64cyc_2X], (instregex "FSQRTv2f64")>; 460 461// ASIMD FP max/min, normal, D-form 462def : InstRW<[A57Write_5cyc_1V], (instregex "^(FMAX|FMIN)(NM)?(v2f32)")>; 463// ASIMD FP max/min, normal, Q-form 464def : InstRW<[A57Write_5cyc_2V], (instregex "^(FMAX|FMIN)(NM)?(v4f32|v2f64)")>; 465// ASIMD FP max/min, pairwise, D-form 466def : InstRW<[A57Write_5cyc_1V], (instregex "^(FMAX|FMIN)(NM)?P(v2f32|v2i32)")>; 467// ASIMD FP max/min, pairwise, Q-form 468def : InstRW<[A57Write_9cyc_3V], (instregex "^(FMAX|FMIN)(NM)?P(v4f32|v2f64|v2i64)")>; 469// ASIMD FP max/min, reduce 470def : InstRW<[A57Write_10cyc_3V], (instregex "^(FMAX|FMIN)(NM)?Vv")>; 471 472// ASIMD FP multiply, D-form, FZ 473def : InstRW<[A57Write_5cyc_1V], (instregex "^FMULX?(v2f32|v1i32|v2i32|v1i64|32|64)")>; 474// ASIMD FP multiply, Q-form, FZ 475def : InstRW<[A57Write_5cyc_2V], (instregex "^FMULX?(v4f32|v2f64|v4i32|v2i64)")>; 476 477// ASIMD FP multiply accumulate, D-form, FZ 478// ASIMD FP multiply accumulate, Q-form, FZ 479def A57WriteFPVMAD : SchedWriteRes<[A57UnitV]> { let Latency = 9; } 480def A57WriteFPVMAQ : SchedWriteRes<[A57UnitV, A57UnitV]> { let Latency = 10; } 481def A57ReadFPVMA5 : SchedReadAdvance<5, [A57WriteFPVMAD, A57WriteFPVMAQ]>; 482def : InstRW<[A57WriteFPVMAD, A57ReadFPVMA5], (instregex "^FML[AS](v2f32|v1i32|v2i32|v1i64)")>; 483def : InstRW<[A57WriteFPVMAQ, A57ReadFPVMA5], (instregex "^FML[AS](v4f32|v2f64|v4i32|v2i64)")>; 484 485// ASIMD FP round, D-form 486def : InstRW<[A57Write_5cyc_1V], (instregex "^FRINT[AIMNPXZ](v2f32)")>; 487// ASIMD FP round, Q-form 488def : InstRW<[A57Write_5cyc_2V], (instregex "^FRINT[AIMNPXZ](v4f32|v2f64)")>; 489 490 491// Vector - Miscellaneous 492// ----------------------------------------------------------------------------- 493 494// Reference for forms in this group 495// D form - v8i8, v4i16, v2i32 496// Q form - v16i8, v8i16, v4i32 497// D form - v1i8, v1i16, v1i32, v1i64 498// Q form - v16i8, v8i16, v4i32, v2i64 499 500// ASIMD bitwise insert, Q-form 501def : InstRW<[A57Write_3cyc_2V], (instregex "^(BIF|BIT|BSL)v16i8")>; 502 503// ASIMD duplicate, gen reg, D-form and Q-form 504def : InstRW<[A57Write_8cyc_1L_1V], (instregex "^CPY")>; 505def : InstRW<[A57Write_8cyc_1L_1V], (instregex "^DUPv.+gpr")>; 506 507// ASIMD move, saturating 508def : InstRW<[A57Write_4cyc_1X], (instregex "^[SU]QXTU?N")>; 509 510// ASIMD reciprocal estimate, D-form 511def : InstRW<[A57Write_5cyc_1V], (instregex "^[FU](RECP|RSQRT)(E|X)(v2f32|v1i32|v2i32|v1i64)")>; 512// ASIMD reciprocal estimate, Q-form 513def : InstRW<[A57Write_5cyc_2V], (instregex "^[FU](RECP|RSQRT)(E|X)(v2f64|v4f32|v4i32)")>; 514 515// ASIMD reciprocal step, D-form, FZ 516def : InstRW<[A57Write_9cyc_1V], (instregex "^F(RECP|RSQRT)S(v2f32|v1i32|v2i32|v1i64|32|64)")>; 517// ASIMD reciprocal step, Q-form, FZ 518def : InstRW<[A57Write_9cyc_2V], (instregex "^F(RECP|RSQRT)S(v2f64|v4f32|v4i32)")>; 519 520// ASIMD table lookup, D-form 521def : InstRW<[A57Write_3cyc_1V], (instregex "^TB[LX]v8i8One")>; 522def : InstRW<[A57Write_6cyc_2V], (instregex "^TB[LX]v8i8Two")>; 523def : InstRW<[A57Write_9cyc_3V], (instregex "^TB[LX]v8i8Three")>; 524def : InstRW<[A57Write_12cyc_4V], (instregex "^TB[LX]v8i8Four")>; 525// ASIMD table lookup, Q-form 526def : InstRW<[A57Write_6cyc_3V], (instregex "^TB[LX]v16i8One")>; 527def : InstRW<[A57Write_9cyc_5V], (instregex "^TB[LX]v16i8Two")>; 528def : InstRW<[A57Write_12cyc_7V], (instregex "^TB[LX]v16i8Three")>; 529def : InstRW<[A57Write_15cyc_9V], (instregex "^TB[LX]v16i8Four")>; 530 531// ASIMD transfer, element to gen reg 532def : InstRW<[A57Write_6cyc_1I_1L], (instregex "^[SU]MOVv")>; 533 534// ASIMD transfer, gen reg to element 535def : InstRW<[A57Write_8cyc_1L_1V], (instregex "^INSv")>; 536 537// ASIMD unzip/zip, Q-form 538def : InstRW<[A57Write_6cyc_3V], (instregex "^(UZP|ZIP)(1|2)(v16i8|v8i16|v4i32|v2i64)")>; 539 540 541// Remainder 542// ----------------------------------------------------------------------------- 543 544def : InstRW<[A57Write_5cyc_1V], (instregex "^F(ADD|SUB)[DS]rr")>; 545 546def A57WriteFPMA : SchedWriteRes<[A57UnitV]> { let Latency = 9; } 547def A57ReadFPMA5 : SchedReadAdvance<5, [A57WriteFPMA]>; 548def A57ReadFPM : SchedReadAdvance<0>; 549def : InstRW<[A57WriteFPMA, A57ReadFPM, A57ReadFPM, A57ReadFPMA5], (instregex "^FN?M(ADD|SUB)[DS]rrr")>; 550 551def : InstRW<[A57Write_10cyc_1L_1V], (instregex "^[FSU]CVT[AMNPZ][SU](_Int)?[SU]?[XW]?[DS]?[rds]i?")>; 552def : InstRW<[A57Write_10cyc_1L_1V], (instregex "^[SU]CVTF")>; 553 554def : InstRW<[A57Write_32cyc_1X], (instrs FDIVDrr)>; 555def : InstRW<[A57Write_18cyc_1X], (instrs FDIVSrr)>; 556 557def : InstRW<[A57Write_5cyc_1V], (instregex "^F(MAX|MIN).+rr")>; 558 559def : InstRW<[A57Write_5cyc_1V], (instregex "^FRINT.+r")>; 560 561def : InstRW<[A57Write_32cyc_1X], (instrs FSQRTDr)>; 562def : InstRW<[A57Write_18cyc_1X], (instrs FSQRTSr)>; 563 564def : InstRW<[A57Write_5cyc_1L, WriteLDHi], (instrs LDNPDi)>; 565def : InstRW<[A57Write_6cyc_2L, WriteLDHi], (instrs LDNPQi)>; 566def : InstRW<[A57Write_5cyc_1L, WriteLDHi], (instrs LDNPSi)>; 567def : InstRW<[A57Write_5cyc_1L, WriteLDHi], (instrs LDPDi)>; 568def : InstRW<[A57Write_5cyc_1L, WriteLDHi, WriteAdr], (instrs LDPDpost)>; 569def : InstRW<[A57Write_5cyc_1L, WriteLDHi, WriteAdr], (instrs LDPDpre)>; 570def : InstRW<[A57Write_6cyc_2L, WriteLDHi], (instrs LDPQi)>; 571def : InstRW<[A57Write_6cyc_2L, WriteLDHi, WriteAdr], (instrs LDPQpost)>; 572def : InstRW<[A57Write_6cyc_2L, WriteLDHi, WriteAdr], (instrs LDPQpre)>; 573def : InstRW<[A57Write_5cyc_1I_2L, WriteLDHi], (instrs LDPSWi)>; 574def : InstRW<[A57Write_5cyc_1I_2L, WriteLDHi, WriteAdr], (instrs LDPSWpost)>; 575def : InstRW<[A57Write_5cyc_1I_2L, WriteLDHi, WriteAdr], (instrs LDPSWpre)>; 576def : InstRW<[A57Write_5cyc_1L, WriteLDHi], (instrs LDPSi)>; 577def : InstRW<[A57Write_5cyc_1L, WriteLDHi, WriteAdr], (instrs LDPSpost)>; 578def : InstRW<[A57Write_5cyc_1L, WriteLDHi, WriteAdr], (instrs LDPSpre)>; 579def : InstRW<[A57Write_5cyc_1L, WriteI], (instrs LDRBpost)>; 580def : InstRW<[A57Write_5cyc_1L, WriteAdr], (instrs LDRBpre)>; 581def : InstRW<[A57Write_5cyc_1L, ReadAdrBase], (instrs LDRBroW)>; 582def : InstRW<[A57Write_5cyc_1L, ReadAdrBase], (instrs LDRBroX)>; 583def : InstRW<[A57Write_5cyc_1L], (instrs LDRBui)>; 584def : InstRW<[A57Write_5cyc_1L], (instrs LDRDl)>; 585def : InstRW<[A57Write_5cyc_1L, WriteI], (instrs LDRDpost)>; 586def : InstRW<[A57Write_5cyc_1L, WriteAdr], (instrs LDRDpre)>; 587def : InstRW<[A57Write_5cyc_1L, ReadAdrBase], (instrs LDRDroW)>; 588def : InstRW<[A57Write_5cyc_1L, ReadAdrBase], (instrs LDRDroX)>; 589def : InstRW<[A57Write_5cyc_1L], (instrs LDRDui)>; 590def : InstRW<[A57Write_5cyc_1I_1L, ReadAdrBase], (instrs LDRHHroW)>; 591def : InstRW<[A57Write_5cyc_1I_1L, ReadAdrBase], (instrs LDRHHroX)>; 592def : InstRW<[A57Write_5cyc_1L, WriteI], (instrs LDRHpost)>; 593def : InstRW<[A57Write_5cyc_1L, WriteAdr], (instrs LDRHpre)>; 594def : InstRW<[A57Write_6cyc_1I_1L, ReadAdrBase], (instrs LDRHroW)>; 595def : InstRW<[A57Write_6cyc_1I_1L, ReadAdrBase], (instrs LDRHroX)>; 596def : InstRW<[A57Write_5cyc_1L], (instrs LDRHui)>; 597def : InstRW<[A57Write_5cyc_1L], (instrs LDRQl)>; 598def : InstRW<[A57Write_5cyc_1L, WriteI], (instrs LDRQpost)>; 599def : InstRW<[A57Write_5cyc_1L, WriteAdr], (instrs LDRQpre)>; 600def : InstRW<[A57Write_6cyc_1I_1L, ReadAdrBase], (instrs LDRQroW)>; 601def : InstRW<[A57Write_6cyc_1I_1L, ReadAdrBase], (instrs LDRQroX)>; 602def : InstRW<[A57Write_5cyc_1L], (instrs LDRQui)>; 603def : InstRW<[A57Write_5cyc_1I_1L, ReadAdrBase], (instrs LDRSHWroW)>; 604def : InstRW<[A57Write_5cyc_1I_1L, ReadAdrBase], (instrs LDRSHWroX)>; 605def : InstRW<[A57Write_5cyc_1I_1L, ReadAdrBase], (instrs LDRSHXroW)>; 606def : InstRW<[A57Write_5cyc_1I_1L, ReadAdrBase], (instrs LDRSHXroX)>; 607def : InstRW<[A57Write_5cyc_1L], (instrs LDRSl)>; 608def : InstRW<[A57Write_5cyc_1L, WriteI], (instrs LDRSpost)>; 609def : InstRW<[A57Write_5cyc_1L, WriteAdr], (instrs LDRSpre)>; 610def : InstRW<[A57Write_5cyc_1L, ReadAdrBase], (instrs LDRSroW)>; 611def : InstRW<[A57Write_5cyc_1L, ReadAdrBase], (instrs LDRSroX)>; 612def : InstRW<[A57Write_5cyc_1L], (instrs LDRSui)>; 613def : InstRW<[A57Write_5cyc_1L], (instrs LDURBi)>; 614def : InstRW<[A57Write_5cyc_1L], (instrs LDURDi)>; 615def : InstRW<[A57Write_5cyc_1L], (instrs LDURHi)>; 616def : InstRW<[A57Write_5cyc_1L], (instrs LDURQi)>; 617def : InstRW<[A57Write_5cyc_1L], (instrs LDURSi)>; 618 619def : InstRW<[A57Write_2cyc_2S], (instrs STNPDi)>; 620def : InstRW<[A57Write_4cyc_1I_4S], (instrs STNPQi)>; 621def : InstRW<[A57Write_2cyc_2S], (instrs STNPXi)>; 622def : InstRW<[A57Write_2cyc_2S], (instrs STPDi)>; 623def : InstRW<[WriteAdr, A57Write_2cyc_1I_2S], (instrs STPDpost)>; 624def : InstRW<[WriteAdr, A57Write_2cyc_1I_2S], (instrs STPDpre)>; 625def : InstRW<[A57Write_4cyc_1I_4S], (instrs STPQi)>; 626def : InstRW<[WriteAdr, A57Write_4cyc_1I_4S], (instrs STPQpost)>; 627def : InstRW<[WriteAdr, A57Write_4cyc_2I_4S], (instrs STPQpre)>; 628def : InstRW<[WriteAdr, A57Write_1cyc_1I_1S], (instrs STPSpost)>; 629def : InstRW<[WriteAdr, A57Write_1cyc_1I_1S], (instrs STPSpre)>; 630def : InstRW<[WriteAdr, A57Write_1cyc_1I_1S], (instrs STPWpost)>; 631def : InstRW<[WriteAdr, A57Write_1cyc_1I_1S], (instrs STPWpre)>; 632def : InstRW<[A57Write_2cyc_2S], (instrs STPXi)>; 633def : InstRW<[WriteAdr, A57Write_2cyc_1I_2S], (instrs STPXpost)>; 634def : InstRW<[WriteAdr, A57Write_2cyc_1I_2S], (instrs STPXpre)>; 635def : InstRW<[WriteAdr, A57Write_1cyc_1I_1S, ReadAdrBase], (instrs STRBBpost)>; 636def : InstRW<[WriteAdr, A57Write_1cyc_1I_1S, ReadAdrBase], (instrs STRBBpre)>; 637def : InstRW<[WriteAdr, A57Write_1cyc_1I_1S, ReadAdrBase], (instrs STRBpost)>; 638def : InstRW<[WriteAdr, A57Write_1cyc_1I_1S], (instrs STRBpre)>; 639def : InstRW<[A57Write_3cyc_1I_1S, ReadAdrBase], (instrs STRBroW)>; 640def : InstRW<[A57Write_3cyc_1I_1S, ReadAdrBase], (instrs STRBroX)>; 641def : InstRW<[WriteAdr, A57Write_1cyc_1I_1S, ReadAdrBase], (instrs STRDpost)>; 642def : InstRW<[WriteAdr, A57Write_1cyc_1I_1S], (instrs STRDpre)>; 643def : InstRW<[WriteAdr, A57Write_1cyc_1I_1S, ReadAdrBase], (instrs STRHHpost)>; 644def : InstRW<[WriteAdr, A57Write_1cyc_1I_1S, ReadAdrBase], (instrs STRHHpre)>; 645def : InstRW<[A57Write_3cyc_1I_1S, ReadAdrBase], (instrs STRHHroW)>; 646def : InstRW<[A57Write_3cyc_1I_1S, ReadAdrBase], (instrs STRHHroX)>; 647def : InstRW<[WriteAdr, A57Write_1cyc_1I_1S, ReadAdrBase], (instrs STRHpost)>; 648def : InstRW<[WriteAdr, A57Write_1cyc_1I_1S], (instrs STRHpre)>; 649def : InstRW<[A57Write_3cyc_1I_1S, ReadAdrBase], (instrs STRHroW)>; 650def : InstRW<[A57Write_3cyc_1I_1S, ReadAdrBase], (instrs STRHroX)>; 651def : InstRW<[WriteAdr, A57Write_2cyc_1I_2S, ReadAdrBase], (instrs STRQpost)>; 652def : InstRW<[WriteAdr, A57Write_2cyc_1I_2S], (instrs STRQpre)>; 653def : InstRW<[A57Write_2cyc_1I_2S, ReadAdrBase], (instrs STRQroW)>; 654def : InstRW<[A57Write_2cyc_1I_2S, ReadAdrBase], (instrs STRQroX)>; 655def : InstRW<[A57Write_2cyc_1I_2S], (instrs STRQui)>; 656def : InstRW<[WriteAdr, A57Write_1cyc_1I_1S, ReadAdrBase], (instrs STRSpost)>; 657def : InstRW<[WriteAdr, A57Write_1cyc_1I_1S], (instrs STRSpre)>; 658def : InstRW<[WriteAdr, A57Write_1cyc_1I_1S, ReadAdrBase], (instrs STRWpost)>; 659def : InstRW<[WriteAdr, A57Write_1cyc_1I_1S, ReadAdrBase], (instrs STRWpre)>; 660def : InstRW<[WriteAdr, A57Write_1cyc_1I_1S, ReadAdrBase], (instrs STRXpost)>; 661def : InstRW<[WriteAdr, A57Write_1cyc_1I_1S, ReadAdrBase], (instrs STRXpre)>; 662def : InstRW<[A57Write_2cyc_2S], (instrs STURQi)>; 663 664} // SchedModel = CortexA57Model 665