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/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/X86/
DX86InstrVecCompiler.td327 def maskzeroupperv32i1 : maskzeroupper<v32i1, VK32>;
333 def : Pat<(v32i1 (insert_subvector (v32i1 immAllZerosV),
336 def : Pat<(v32i1 (insert_subvector (v32i1 immAllZerosV),
339 def : Pat<(v32i1 (insert_subvector (v32i1 immAllZerosV),
391 def : Pat<(v32i1 (insert_subvector (v32i1 immAllZerosV),
394 def : Pat<(v32i1 (insert_subvector (v32i1 immAllZerosV),
451 def : Pat<(v32i1 (insert_subvector (v32i1 immAllZerosV),
459 (v32i1 VK32:$mask), (iPTR 0))),
464 def : Pat<(v32i1 (insert_subvector (v32i1 immAllZerosV),
476 def : Pat<(v32i1 (insert_subvector (v32i1 immAllZerosV),
[all …]
DX86CallingConv.td85 // Promote v8i1/v16i1/v32i1 arguments to i32.
86 CCIfType<[v8i1, v16i1, v32i1], CCPromoteToType<i32>>,
161 // Promote v32i1 arguments to i32.
162 CCIfType<[v32i1], CCPromoteToType<i32>>,
230 CCIfType<[v32i1], CCPromoteToType<v32i8>>,
531 CCIfType<[v32i1], CCPromoteToType<v32i8>>,
807 CCIfType<[v32i1], CCPromoteToType<v32i8>>,
DX86RegisterInfo.td579 def VK32 : RegisterClass<"X86", [v32i1], 32, (add VK16)> {let Size = 32;}
587 def VK32WM : RegisterClass<"X86", [v32i1], 32, (add VK16WM)> {let Size = 32;}
DX86ISelLowering.cpp1029 setOperationAction(ISD::BITCAST, MVT::v32i1, Custom); in X86TargetLowering()
1485 addRegisterClass(MVT::v32i1, &X86::VK32RegClass); in X86TargetLowering()
1488 for (auto VT : { MVT::v32i1, MVT::v64i1 }) { in X86TargetLowering()
1503 setOperationAction(ISD::CONCAT_VECTORS, MVT::v32i1, Custom); in X86TargetLowering()
1505 setOperationAction(ISD::INSERT_SUBVECTOR, MVT::v32i1, Custom); in X86TargetLowering()
1507 for (auto VT : { MVT::v16i1, MVT::v32i1 }) in X86TargetLowering()
1791 if (VT == MVT::v32i1 && Subtarget.hasAVX512() && !Subtarget.hasBWI()) in getPreferredVectorAction()
1805 if (VT == MVT::v32i1 && Subtarget.hasAVX512() && !Subtarget.hasBWI()) in getRegisterTypeForCallingConv()
1813 if (VT == MVT::v32i1 && Subtarget.hasAVX512() && !Subtarget.hasBWI()) in getNumRegistersForCallingConv()
2238 if ((ValVT == MVT::v32i1 && ValLoc == MVT::i32) || in lowerMasksToReg()
[all …]
DX86InstrAVX512.td184 def v32i1_info : X86KVectorVTInfo<VK32, VK32WM, v32i1>;
2854 defm KMOVD : avx512_mask_mov<0x90, 0x90, 0x91, "kmovd", VK32, v32i1,i32mem>,
2885 def : Pat<(v32i1 (bitconvert (i32 GR32:$src))),
2887 def : Pat<(i32 (bitconvert (v32i1 VK32:$src))),
2926 defm : operation_gpr_mask_copy_lowering<VK32, v32i1>;
3067 defm KUNPCKWD : avx512_mask_unpck<"wd", VK32, v32i1, VK16, WriteShuffle, HasBWI>, PS;
3272 defm D : avx512_mask_setop<VK32, v32i1, Val>;
3304 defm : operation_subvector_mask_lowering<VK1, v1i1, VK32, v32i1>;
3310 defm : operation_subvector_mask_lowering<VK2, v2i1, VK32, v32i1>;
3315 defm : operation_subvector_mask_lowering<VK4, v4i1, VK32, v32i1>;
[all …]
/external/llvm/include/llvm/CodeGen/
DMachineValueType.h63 v32i1 = 17, // 32 x i1 enumerator
321 case v32i1: in getVectorElementType()
384 case v32i1: in getVectorNumElements()
461 case v32i1: in getSizeInBits()
597 if (NumElements == 32) return MVT::v32i1; in getVectorVT()
DValueTypes.td40 def v32i1 : ValueType<32 , 17>; // 32 x i1 vector value
/external/swiftshader/third_party/llvm-7.0/llvm/include/llvm/Support/
DMachineValueType.h65 v32i1 = 19, // 32 x i1 enumerator
337 return (SimpleTy == MVT::v32i1 || SimpleTy == MVT::v4i8 || in is32BitVector()
425 case v32i1: in getVectorElementType()
532 case v32i1: in getVectorNumElements()
665 case v32i1: in getSizeInBits()
837 if (NumElements == 32) return MVT::v32i1; in getVectorVT()
/external/swiftshader/third_party/llvm-7.0/llvm/lib/CodeGen/
DValueTypes.cpp145 case MVT::v32i1: return "v32i1"; in getEVTString()
226 case MVT::v32i1: return VectorType::get(Type::getInt1Ty(Context), 32); in getTypeForEVT()
/external/llvm/lib/IR/
DValueTypes.cpp149 case MVT::v32i1: return "v32i1"; in getEVTString()
227 case MVT::v32i1: return VectorType::get(Type::getInt1Ty(Context), 32); in getTypeForEVT()
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Hexagon/
DHexagonRegisterInfo.td292 [v32i1, v64i1, v32i1]>;
294 [v16i1, v32i1, v16i1]>;
DHexagonISelLoweringHVX.cpp41 addRegisterClass(MVT::v32i1, &Hexagon::HvxQRRegClass); in initializeHVXLowering()
51 addRegisterClass(MVT::v32i1, &Hexagon::HvxQRRegClass); in initializeHVXLowering()
/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/X86/
Davx512-regcall-Mask.ll285 ; Test regcall when receiving arguments of v32i1 type
399 ; Test regcall when passing arguments of v32i1 type
453 ; Test regcall when returning v32i1 type
468 ; Test regcall when processing result of v32i1 type
/external/swiftshader/third_party/llvm-7.0/llvm/include/llvm/CodeGen/
DValueTypes.td41 def v32i1 : ValueType<32 , 19>; // 32 x i1 vector value
/external/llvm/utils/TableGen/
DCodeGenTarget.cpp77 case MVT::v32i1: return "MVT::v32i1"; in getEnumName()
/external/llvm/lib/Target/X86/
DX86CallingConv.td50 CCIfType<[v32i1], CCPromoteToType<v32i8>>,
327 CCIfType<[v32i1], CCPromoteToType<v32i8>>,
600 CCIfType<[v32i1], CCPromoteToType<v32i8>>,
DX86RegisterInfo.td516 def VK32 : RegisterClass<"X86", [v32i1], 32, (add VK16)> {let Size = 32;}
524 def VK32WM : RegisterClass<"X86", [v32i1], 32, (add VK16WM)> {let Size = 32;}
DX86InstrAVX512.td1984 defm KMOVD : avx512_mask_mov<0x90, 0x90, 0x91, "kmovd", VK32, v32i1,i32mem>,
2016 def : Pat<(v32i1 (bitconvert (i32 GR32:$src))), (KMOVDkr GR32:$src)>;
2017 def : Pat<(i32 (bitconvert (v32i1 VK32:$src))), (KMOVDrk VK32:$src)>;
2078 def : Pat<(store (i32 (bitconvert (v32i1 VK32:$src))), addr:$dst),
2080 def : Pat<(v32i1 (bitconvert (i32 (load addr:$src)))),
2156 def : Pat<(v32i1 (scalar_to_vector VK1:$src)),
2233 def : Pat<(xor VK32:$src1, (v32i1 immAllOnesV)), (KNOTDrr VK32:$src1)>;
2334 def : Pat<(xor (xor VK32:$src1, VK32:$src2), (v32i1 immAllOnesV)),
2374 defm KUNPCKWD : avx512_mask_unpck<"wd", VK32, v32i1, VK16, HasBWI>, PS;
2440 defm D : avx512_mask_setop<VK32, v32i1, Val>;
[all …]
DX86ISelLowering.cpp1391 MVT::v16i1, MVT::v32i1, MVT::v64i1 }) in X86TargetLowering()
1416 addRegisterClass(MVT::v32i1, &X86::VK32RegClass); in X86TargetLowering()
1419 setOperationAction(ISD::ADD, MVT::v32i1, Expand); in X86TargetLowering()
1421 setOperationAction(ISD::SUB, MVT::v32i1, Expand); in X86TargetLowering()
1423 setOperationAction(ISD::MUL, MVT::v32i1, Expand); in X86TargetLowering()
1426 setOperationAction(ISD::SETCC, MVT::v32i1, Custom); in X86TargetLowering()
1432 setOperationAction(ISD::CONCAT_VECTORS, MVT::v32i1, Custom); in X86TargetLowering()
1436 setOperationAction(ISD::INSERT_SUBVECTOR, MVT::v32i1, Custom); in X86TargetLowering()
1444 setOperationAction(ISD::SELECT, MVT::v32i1, Custom); in X86TargetLowering()
1455 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v32i1, Custom); in X86TargetLowering()
[all …]
/external/swiftshader/third_party/llvm-7.0/configs/common/lib/Target/X86/
DX86GenCallingConv.inc514 if (LocVT == MVT::v32i1) {
827 LocVT == MVT::v32i1) {
1522 if (LocVT == MVT::v32i1) {
1901 LocVT == MVT::v32i1) {
2333 LocVT == MVT::v32i1) {
2738 if (LocVT == MVT::v32i1) {
3014 if (LocVT == MVT::v32i1) {
3584 if (LocVT == MVT::v32i1) {
3784 if (LocVT == MVT::v32i1) {
DX86GenGlobalISel.inc3736 … (and:{ *:[v32i1] } VK32:{ *:[v32i1] }:$src1, VK32:{ *:[v32i1] }:$src2) => (KANDDrr:{ *:[v32i1] …
4814 …// (or:{ *:[v32i1] } VK32:{ *:[v32i1] }:$src1, VK32:{ *:[v32i1] }:$src2) => (KORDrr:{ *:[v32i1] …
5639 … (xor:{ *:[v32i1] } VK32:{ *:[v32i1] }:$src1, VK32:{ *:[v32i1] }:$src2) => (KXORDrr:{ *:[v32i1] …
5752 …// (bitconvert:{ *:[i32] } VK32:{ *:[v32i1] }:$src) => (COPY_TO_REGCLASS:{ *:[i32] } VK32:{ *:[v…
6835 …// (bitconvert:{ *:[v32i1] } GR32:{ *:[i32] }:$src) => (COPY_TO_REGCLASS:{ *:[v32i1] } GR32:{ *:…
11241 …// (sext:{ *:[v32i8] } VK32:{ *:[v32i1] }:$src) => (VPMOVM2BZ256rr:{ *:[v32i8] } VK32:{ *:[v32i1…
11254 …// (sext:{ *:[v32i16] } VK32:{ *:[v32i1] }:$src) => (VPMOVM2WZrr:{ *:[v32i16] } VK32:{ *:[v32i1]…
DX86GenFastISel.inc1650 case MVT::v32i1: return fastEmit_ISD_SIGN_EXTEND_MVT_v32i1_r(RetVT, Op0, Op0IsKill);
5802 if (RetVT.SimpleTy != MVT::v32i1)
5866 case MVT::v32i1: return fastEmit_ISD_AND_MVT_v32i1_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
6683 if (RetVT.SimpleTy != MVT::v32i1)
6747 case MVT::v32i1: return fastEmit_ISD_OR_MVT_v32i1_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
8139 if (RetVT.SimpleTy != MVT::v32i1)
8203 case MVT::v32i1: return fastEmit_ISD_XOR_MVT_v32i1_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
9648 if (RetVT.SimpleTy != MVT::v32i1)
9669 case MVT::v32i1: return fastEmit_X86ISD_KADD_MVT_v32i1_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
9717 …case MVT::v32i1: return fastEmit_X86ISD_KORTEST_MVT_v32i1_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill…
[all …]
/external/swiftshader/third_party/llvm-7.0/llvm/utils/TableGen/
DCodeGenTarget.cpp84 case MVT::v32i1: return "MVT::v32i1"; in getEnumName()
/external/llvm/include/llvm/IR/
DIntrinsics.td173 def llvm_v32i1_ty : LLVMType<v32i1>; // 32 x i1
/external/swiftshader/third_party/llvm-7.0/llvm/include/llvm/IR/
DIntrinsics.td201 def llvm_v32i1_ty : LLVMType<v32i1>; // 32 x i1

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