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Searched refs:v32i32 (Results 1 – 25 of 38) sorted by relevance

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/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Hexagon/
DHexagonCallingConv.td89 CCIfType<[v32i32,v64i16,v128i8],
95 CCIfType<[v32i32,v64i16,v128i8],
100 CCIfType<[v32i32,v64i16,v128i8],
106 CCIfType<[v32i32,v64i16,v128i8],
121 CCIfType<[v32i32,v64i16,v128i8],
126 CCIfType<[v32i32,v64i16,v128i8],
DHexagonIntrinsicsV60.td16 def : Pat < (v16i32 (int_hexagon_V6_lo (v32i32 HvxWR:$src1))),
17 (v16i32 (EXTRACT_SUBREG (v32i32 HvxWR:$src1), vsub_lo)) >;
19 def : Pat < (v16i32 (int_hexagon_V6_hi (v32i32 HvxWR:$src1))),
20 (v16i32 (EXTRACT_SUBREG (v32i32 HvxWR:$src1), vsub_hi)) >;
22 def : Pat < (v32i32 (int_hexagon_V6_lo_128B (v64i32 HvxWR:$src1))),
23 (v32i32 (EXTRACT_SUBREG (v64i32 HvxWR:$src1), vsub_lo)) >;
25 def : Pat < (v32i32 (int_hexagon_V6_hi_128B (v64i32 HvxWR:$src1))),
26 (v32i32 (EXTRACT_SUBREG (v64i32 HvxWR:$src1), vsub_hi)) >;
47 def : Pat <(v1024i1 (bitconvert (v32i32 HvxVR:$src1))),
48 (v1024i1 (V6_vandvrt (v32i32 HvxVR:$src1), (A2_tfrsi 0x01010101)))>;
[all …]
DHexagonRegisterInfo.td280 [v16i32, v32i32, v16i32]>;
287 [v32i32, v64i32, v32i32]>;
DHexagonISelLoweringHVX.cpp18 static const MVT LegalW64[] = { MVT::v128i8, MVT::v64i16, MVT::v32i32 };
19 static const MVT LegalV128[] = { MVT::v128i8, MVT::v64i16, MVT::v32i32 };
31 addRegisterClass(MVT::v32i32, &Hexagon::HvxWRRegClass); in initializeHVXLowering()
47 addRegisterClass(MVT::v32i32, &Hexagon::HvxVRRegClass); in initializeHVXLowering()
DHexagonISelDAGToDAGHVX.cpp2149 SDVTList VTs = CurDAG->getVTList(MVT::v32i32, MVT::v1024i1); in SelectHVXDualOutput()
2163 SDVTList VTs = CurDAG->getVTList(MVT::v32i32, MVT::v1024i1); in SelectHVXDualOutput()
/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/Hexagon/autohvx/
Dbitcount-128b.ll25 %t0 = call <32 x i32> @llvm.ctpop.v32i32(<32 x i32> %a0)
52 %t0 = call <32 x i32> @llvm.ctlz.v32i32(<32 x i32> %a0)
108 %t0 = call <32 x i32> @llvm.cttz.v32i32(<32 x i32> %a0)
114 declare <32 x i32> @llvm.ctpop.v32i32(<32 x i32>) #0
118 declare <32 x i32> @llvm.ctlz.v32i32(<32 x i32>) #0
122 declare <32 x i32> @llvm.cttz.v32i32(<32 x i32>) #0
Dbswap.ll35 %v0 = call <32 x i32> @llvm.bswap.v32i32(<32 x i32> %a0)
42 declare <32 x i32> @llvm.bswap.v32i32(<32 x i32>) #1
/external/llvm/lib/Target/Hexagon/
DHexagonIntrinsicsV60.td65 def : Pat < (v16i32 (int_hexagon_V6_lo (v32i32 VecDblRegs:$src1))),
66 (v16i32 (EXTRACT_SUBREG (v32i32 VecDblRegs:$src1), subreg_loreg)) >,
69 def : Pat < (v16i32 (int_hexagon_V6_hi (v32i32 VecDblRegs:$src1))),
70 (v16i32 (EXTRACT_SUBREG (v32i32 VecDblRegs:$src1), subreg_hireg)) >,
73 def : Pat < (v32i32 (int_hexagon_V6_lo_128B (v64i32 VecDblRegs128B:$src1))),
74 (v32i32 (EXTRACT_SUBREG (v64i32 VecDblRegs128B:$src1),
78 def : Pat < (v32i32 (int_hexagon_V6_hi_128B (v64i32 VecDblRegs128B:$src1))),
79 (v32i32 (EXTRACT_SUBREG (v64i32 VecDblRegs128B:$src1),
124 def : Pat <(v1024i1 (bitconvert (v32i32 VectorRegs128B:$src1))),
125 (v1024i1 (V6_vandvrt_128B(v32i32 VectorRegs128B:$src1),
[all …]
DHexagonISelLowering.cpp203 if (LocVT == MVT::v16i64 || LocVT == MVT::v32i32 || LocVT == MVT::v64i16 || in CC_Hexagon_VarArg()
348 (LocVT == MVT::v16i64 || LocVT == MVT::v32i32 || LocVT == MVT::v64i16 || in CC_HexagonVector()
371 (LocVT == MVT::v16i64 || LocVT == MVT::v32i32 || LocVT == MVT::v64i16 || in CC_HexagonVector()
419 LocVT == MVT::v32i32 || LocVT == MVT::v16i64 || in RetCC_Hexagon()
421 LocVT = MVT::v32i32; in RetCC_Hexagon()
422 ValVT = MVT::v32i32; in RetCC_Hexagon()
439 if (LocVT == MVT::v16i32 || LocVT == MVT::v32i32 || LocVT == MVT::v64i32) { in RetCC_Hexagon()
490 } else if (LocVT == MVT::v32i32) { in RetCC_HexagonVector()
545 ty == MVT::v16i64 || ty == MVT::v32i32 || ty == MVT::v64i16 || in IsHvxVectorType()
898 (UseHVX && UseHVXDbl) && (VT == MVT::v32i32 || VT == MVT::v16i64 || in getIndexedAddressParts()
[all …]
DHexagonRegisterInfo.td230 [v128i8, v64i16, v32i32, v16i64], 1024,
234 [v128i8, v64i16, v32i32, v16i64], 1024,
DHexagonInstrInfoV60.td800 defm : STrivv_pats <v32i32, v64i32>;
850 defm : vS32b_ai_pats <v16i32, v32i32>;
875 defm : LDrivv_pats <v32i32, v64i32>;
915 defm : vL32b_ai_pats <v16i32, v32i32>;
1589 def: Pat<(v32i32 (HexagonVCOMBINE (v16i32 VectorRegs:$Vs),
1593 def: Pat<(v64i32 (HexagonVCOMBINE (v32i32 VecDblRegs:$Vs),
1594 (v32i32 VecDblRegs:$Vt))),
DHexagonISelDAGToDAG.cpp287 case MVT::v32i32: in SelectIndexedLoad()
575 case MVT::v32i32: in SelectIndexedStore()
/external/llvm/include/llvm/CodeGen/
DMachineValueType.h92 v32i32 = 43, // 32 x i32 enumerator
273 SimpleTy == MVT::v64i16 || SimpleTy == MVT::v32i32 || in is1024BitVector()
347 case v32i32: in getVectorElementType()
387 case v32i32: in getVectorNumElements()
506 case v32i32: in getSizeInBits()
629 if (NumElements == 32) return MVT::v32i32; in getVectorVT()
DValueTypes.td69 def v32i32 : ValueType<1024,43>; // 32 x i32 vector value
/external/swiftshader/third_party/llvm-7.0/llvm/include/llvm/Support/
DMachineValueType.h95 v32i32 = 46, // 32 x i32 enumerator
377 SimpleTy == MVT::v64i16 || SimpleTy == MVT::v32i32 || in is1024BitVector()
470 case v32i32: in getVectorElementType()
535 case v32i32: in getVectorNumElements()
742 case v32i32: in getSizeInBits()
870 if (NumElements == 32) return MVT::v32i32; in getVectorVT()
/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/Hexagon/
Dbitconvert-vector.ll3 ; This testcase would fail on a bitcast from v64i16 to v32i32. Check that
/external/llvm/test/CodeGen/Hexagon/
Dbitconvert-vector.ll3 ; This testcase would fail on a bitcast from v64i16 to v32i32. Check that
/external/swiftshader/third_party/llvm-7.0/llvm/lib/CodeGen/
DValueTypes.cpp172 case MVT::v32i32: return "v32i32"; in getEVTString()
253 case MVT::v32i32: return VectorType::get(Type::getInt32Ty(Context), 32); in getTypeForEVT()
/external/llvm/lib/IR/
DValueTypes.cpp175 case MVT::v32i32: return "v32i32"; in getEVTString()
253 case MVT::v32i32: return VectorType::get(Type::getInt32Ty(Context), 32); in getTypeForEVT()
/external/swiftshader/third_party/llvm-7.0/llvm/include/llvm/CodeGen/
DValueTypes.td71 def v32i32 : ValueType<1024,46>; // 32 x i32 vector value
/external/llvm/utils/TableGen/
DCodeGenTarget.cpp103 case MVT::v32i32: return "MVT::v32i32"; in getEnumName()
/external/swiftshader/third_party/llvm-7.0/llvm/utils/TableGen/
DCodeGenTarget.cpp111 case MVT::v32i32: return "MVT::v32i32"; in getEnumName()
/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/X86/
Dvector-reduce-and.ll387 %1 = call i32 @llvm.experimental.vector.reduce.and.i32.v32i32(<32 x i32> %a0)
1018 declare i32 @llvm.experimental.vector.reduce.and.i32.v32i32(<32 x i32>)
Dvector-reduce-or.ll387 %1 = call i32 @llvm.experimental.vector.reduce.or.i32.v32i32(<32 x i32> %a0)
1018 declare i32 @llvm.experimental.vector.reduce.or.i32.v32i32(<32 x i32>)
Dvector-reduce-xor.ll387 %1 = call i32 @llvm.experimental.vector.reduce.xor.i32.v32i32(<32 x i32> %a0)
1018 declare i32 @llvm.experimental.vector.reduce.xor.i32.v32i32(<32 x i32>)

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