| /external/llvm/lib/Target/Hexagon/ |
| D | HexagonIntrinsicsV60.td | 84 def : Pat <(v512i1 (bitconvert (v16i32 VectorRegs:$src1))),
85 (v512i1 (V6_vandvrt(v16i32 VectorRegs:$src1),
89 def : Pat <(v512i1 (bitconvert (v32i16 VectorRegs:$src1))),
90 (v512i1 (V6_vandvrt(v32i16 VectorRegs:$src1),
94 def : Pat <(v512i1 (bitconvert (v64i8 VectorRegs:$src1))),
95 (v512i1 (V6_vandvrt(v64i8 VectorRegs:$src1),
99 def : Pat <(v512i1 (bitconvert (v8i64 VectorRegs:$src1))),
100 (v512i1 (V6_vandvrt(v8i64 VectorRegs:$src1),
104 def : Pat <(v16i32 (bitconvert (v512i1 VecPredRegs:$src1))),
105 (v16i32 (V6_vandqrt(v512i1 VecPredRegs:$src1),
[all …]
|
| D | HexagonISelLowering.cpp | 198 LocVT == MVT::v64i8 || LocVT == MVT::v512i1) { in CC_Hexagon_VarArg()
338 LocVT == MVT::v64i8 || LocVT == MVT::v512i1)) { in CC_HexagonVector()
414 LocVT == MVT::v512i1) { in RetCC_Hexagon()
549 ty == MVT::v512i1 || ty == MVT::v1024i1); in IsHvxVectorType()
1146 } else if (RegVT == MVT::v512i1 || RegVT == MVT::v1024i1) { in LowerFormalArguments()
1763 addRegisterClass(MVT::v512i1, &Hexagon::VecPredRegsRegClass); in HexagonTargetLowering()
2872 case MVT::v512i1: in getRegForInlineAsmConstraint()
|
| D | HexagonRegisterInfo.td | 241 def VecPredRegs : RegisterClass<"Hexagon", [v512i1], 512,
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Hexagon/ |
| D | HexagonIntrinsicsV60.td | 29 def : Pat <(v512i1 (bitconvert (v16i32 HvxVR:$src1))),
30 (v512i1 (V6_vandvrt(v16i32 HvxVR:$src1), (A2_tfrsi 0x01010101)))>;
32 def : Pat <(v512i1 (bitconvert (v32i16 HvxVR:$src1))),
33 (v512i1 (V6_vandvrt(v32i16 HvxVR:$src1), (A2_tfrsi 0x01010101)))>;
35 def : Pat <(v512i1 (bitconvert (v64i8 HvxVR:$src1))),
36 (v512i1 (V6_vandvrt(v64i8 HvxVR:$src1), (A2_tfrsi 0x01010101)))>;
38 def : Pat <(v16i32 (bitconvert (v512i1 HvxQR:$src1))),
39 (v16i32 (V6_vandqrt(v512i1 HvxQR:$src1), (A2_tfrsi 0x01010101)))>;
41 def : Pat <(v32i16 (bitconvert (v512i1 HvxQR:$src1))),
42 (v32i16 (V6_vandqrt(v512i1 HvxQR:$src1), (A2_tfrsi 0x01010101)))>;
[all …]
|
| D | HexagonRegisterInfo.td | 274 [v512i1, v1024i1, v512i1]>;
|
| D | HexagonISelDAGToDAGHVX.cpp | 2142 SDVTList VTs = CurDAG->getVTList(MVT::v16i32, MVT::v512i1); in SelectHVXDualOutput()
2156 SDVTList VTs = CurDAG->getVTList(MVT::v16i32, MVT::v512i1); in SelectHVXDualOutput()
|
| D | HexagonISelLoweringHVX.cpp | 43 addRegisterClass(MVT::v512i1, &Hexagon::HvxQRRegClass); in initializeHVXLowering()
|
| /external/llvm/include/llvm/CodeGen/ |
| D | MachineValueType.h | 65 v512i1 = 19, // 512 x i1 enumerator
265 SimpleTy == MVT::v512i1 || SimpleTy == MVT::v64i8 || in is512BitVector()
323 case v512i1: in getVectorElementType()
376 case v512i1: return 512; in getVectorNumElements()
496 case v512i1: in getSizeInBits()
599 if (NumElements == 512) return MVT::v512i1; in getVectorVT()
|
| D | ValueTypes.td | 42 def v512i1 : ValueType<512, 19>; // 512 x i1 vector value
|
| /external/swiftshader/third_party/llvm-7.0/llvm/include/llvm/Support/ |
| D | MachineValueType.h | 68 v512i1 = 22, // 512 x i1 enumerator
369 SimpleTy == MVT::v512i1 || SimpleTy == MVT::v64i8 || in is512BitVector()
428 case v512i1: in getVectorElementType()
523 case v512i1: return 512; in getVectorNumElements()
727 case v512i1: in getSizeInBits()
840 if (NumElements == 512) return MVT::v512i1; in getVectorVT()
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/CodeGen/ |
| D | ValueTypes.cpp | 148 case MVT::v512i1: return "v512i1"; in getEVTString()
229 case MVT::v512i1: return VectorType::get(Type::getInt1Ty(Context), 512); in getTypeForEVT()
|
| /external/llvm/lib/IR/ |
| D | ValueTypes.cpp | 151 case MVT::v512i1: return "v512i1"; in getEVTString()
229 case MVT::v512i1: return VectorType::get(Type::getInt1Ty(Context), 512); in getTypeForEVT()
|
| /external/swiftshader/third_party/llvm-7.0/llvm/include/llvm/CodeGen/ |
| D | ValueTypes.td | 44 def v512i1 : ValueType<512, 22>; // 512 x i1 vector value
|
| /external/llvm/utils/TableGen/ |
| D | CodeGenTarget.cpp | 79 case MVT::v512i1: return "MVT::v512i1"; in getEnumName()
|
| /external/swiftshader/third_party/llvm-7.0/llvm/utils/TableGen/ |
| D | CodeGenTarget.cpp | 87 case MVT::v512i1: return "MVT::v512i1"; in getEnumName()
|
| /external/llvm/include/llvm/IR/ |
| D | Intrinsics.td | 175 def llvm_v512i1_ty : LLVMType<v512i1>; // 512 x i1
|
| /external/swiftshader/third_party/llvm-7.0/llvm/include/llvm/IR/ |
| D | Intrinsics.td | 203 def llvm_v512i1_ty : LLVMType<v512i1>; // 512 x i1
|