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Searched refs:v64i16 (Results 1 – 25 of 35) sorted by relevance

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/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Hexagon/
DHexagonCallingConv.td89 CCIfType<[v32i32,v64i16,v128i8],
95 CCIfType<[v32i32,v64i16,v128i8],
100 CCIfType<[v32i32,v64i16,v128i8],
106 CCIfType<[v32i32,v64i16,v128i8],
121 CCIfType<[v32i32,v64i16,v128i8],
126 CCIfType<[v32i32,v64i16,v128i8],
DHexagonIntrinsicsV60.td50 def : Pat <(v1024i1 (bitconvert (v64i16 HvxVR:$src1))),
51 (v1024i1 (V6_vandvrt (v64i16 HvxVR:$src1), (A2_tfrsi 0x01010101)))>;
59 def : Pat <(v64i16 (bitconvert (v1024i1 HvxQR:$src1))),
60 (v64i16 (V6_vandqrt (v1024i1 HvxQR:$src1), (A2_tfrsi 0x01010101)))>;
636 def: Pat<(v64i16 (trunc v64i32:$Vdd)),
637 (v64i16 (V6_vpackwh_sat
DHexagonRegisterInfo.td278 [v32i16, v64i16, v32i16]>;
285 [v64i16, v128i16, v64i16]>;
DHexagonISelLoweringHVX.cpp18 static const MVT LegalW64[] = { MVT::v128i8, MVT::v64i16, MVT::v32i32 };
19 static const MVT LegalV128[] = { MVT::v128i8, MVT::v64i16, MVT::v32i32 };
30 addRegisterClass(MVT::v64i16, &Hexagon::HvxWRRegClass); in initializeHVXLowering()
46 addRegisterClass(MVT::v64i16, &Hexagon::HvxVRRegClass); in initializeHVXLowering()
DHexagonISelDAGToDAG.cpp113 case MVT::v64i16: in SelectIndexedLoad()
505 case MVT::v64i16: in SelectIndexedStore()
/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/Hexagon/autohvx/
Dbitcount-128b.ll16 %t0 = call <64 x i16> @llvm.ctpop.v64i16(<64 x i16> %a0)
45 %t0 = call <64 x i16> @llvm.ctlz.v64i16(<64 x i16> %a0)
92 %t0 = call <64 x i16> @llvm.cttz.v64i16(<64 x i16> %a0)
113 declare <64 x i16> @llvm.ctpop.v64i16(<64 x i16>) #0
117 declare <64 x i16> @llvm.ctlz.v64i16(<64 x i16>) #0
121 declare <64 x i16> @llvm.cttz.v64i16(<64 x i16>) #0
Dbswap.ll26 %v0 = call <64 x i16> @llvm.bswap.v64i16(<64 x i16> %a0)
41 declare <64 x i16> @llvm.bswap.v64i16(<64 x i16>) #1
/external/llvm/include/llvm/CodeGen/
DMachineValueType.h84 v64i16 = 36, // 64 x i16 enumerator
273 SimpleTy == MVT::v64i16 || SimpleTy == MVT::v32i32 || in is1024BitVector()
340 case v64i16: in getVectorElementType()
382 case v64i16: in getVectorNumElements()
505 case v64i16: in getSizeInBits()
620 if (NumElements == 64) return MVT::v64i16; in getVectorVT()
DValueTypes.td61 def v64i16 : ValueType<1024,36>; // 64 x i16 vector value
/external/swiftshader/third_party/llvm-7.0/llvm/include/llvm/Support/
DMachineValueType.h87 v64i16 = 39, // 64 x i16 enumerator
377 SimpleTy == MVT::v64i16 || SimpleTy == MVT::v32i32 || in is1024BitVector()
457 case v64i16: in getVectorElementType()
530 case v64i16: in getVectorNumElements()
741 case v64i16: in getSizeInBits()
861 if (NumElements == 64) return MVT::v64i16; in getVectorVT()
/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/Hexagon/
Dbitconvert-vector.ll3 ; This testcase would fail on a bitcast from v64i16 to v32i32. Check that
/external/llvm/test/CodeGen/Hexagon/
Dbitconvert-vector.ll3 ; This testcase would fail on a bitcast from v64i16 to v32i32. Check that
/external/llvm/lib/Target/Hexagon/
DHexagonIntrinsicsV60.td129 def : Pat <(v1024i1 (bitconvert (v64i16 VectorRegs128B:$src1))),
130 (v1024i1 (V6_vandvrt_128B(v64i16 VectorRegs128B:$src1),
149 def : Pat <(v64i16 (bitconvert (v1024i1 VecPredRegs128B:$src1))),
150 (v64i16 (V6_vandqrt_128B(v1024i1 VecPredRegs128B:$src1),
832 def: Pat<(v64i16 (trunc v64i32:$Vdd)),
833 (v64i16 (V6_vpackwh_sat_128B
DHexagonISelLowering.cpp203 if (LocVT == MVT::v16i64 || LocVT == MVT::v32i32 || LocVT == MVT::v64i16 || in CC_Hexagon_VarArg()
348 (LocVT == MVT::v16i64 || LocVT == MVT::v32i32 || LocVT == MVT::v64i16 || in CC_HexagonVector()
371 (LocVT == MVT::v16i64 || LocVT == MVT::v32i32 || LocVT == MVT::v64i16 || in CC_HexagonVector()
418 } else if (LocVT == MVT::v128i8 || LocVT == MVT::v64i16 || in RetCC_Hexagon()
545 ty == MVT::v16i64 || ty == MVT::v32i32 || ty == MVT::v64i16 || in IsHvxVectorType()
899 VT == MVT::v64i16 || VT == MVT::v128i8); in getIndexedAddressParts()
1126 RegVT == MVT::v64i16 || RegVT == MVT::v128i8))) { in LowerFormalArguments()
1134 RegVT == MVT::v64i16 || RegVT == MVT::v128i8)) { in LowerFormalArguments()
1760 addRegisterClass(MVT::v64i16, &Hexagon::VecDblRegsRegClass); in HexagonTargetLowering()
1766 addRegisterClass(MVT::v64i16, &Hexagon::VectorRegs128BRegClass); in HexagonTargetLowering()
[all …]
DHexagonRegisterInfo.td230 [v128i8, v64i16, v32i32, v16i64], 1024,
234 [v128i8, v64i16, v32i32, v16i64], 1024,
DHexagonISelDAGToDAG.cpp286 case MVT::v64i16: in SelectIndexedLoad()
574 case MVT::v64i16: in SelectIndexedStore()
DHexagonInstrInfoV60.td799 defm : STrivv_pats <v64i16, v128i16>;
849 defm : vS32b_ai_pats <v32i16, v64i16>;
874 defm : LDrivv_pats <v64i16, v128i16>;
914 defm : vL32b_ai_pats <v32i16, v64i16>;
/external/swiftshader/third_party/llvm-7.0/llvm/lib/CodeGen/
DValueTypes.cpp165 case MVT::v64i16: return "v64i16"; in getEVTString()
246 case MVT::v64i16: return VectorType::get(Type::getInt16Ty(Context), 64); in getTypeForEVT()
/external/llvm/lib/IR/
DValueTypes.cpp168 case MVT::v64i16: return "v64i16"; in getEVTString()
246 case MVT::v64i16: return VectorType::get(Type::getInt16Ty(Context), 64); in getTypeForEVT()
/external/swiftshader/third_party/llvm-7.0/llvm/include/llvm/CodeGen/
DValueTypes.td63 def v64i16 : ValueType<1024,39>; // 64 x i16 vector value
/external/llvm/utils/TableGen/
DCodeGenTarget.cpp96 case MVT::v64i16: return "MVT::v64i16"; in getEnumName()
/external/swiftshader/third_party/llvm-7.0/llvm/utils/TableGen/
DCodeGenTarget.cpp104 case MVT::v64i16: return "MVT::v64i16"; in getEnumName()
/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/X86/
Dvector-reduce-and.ll642 %1 = call i16 @llvm.experimental.vector.reduce.and.i16.v64i16(<64 x i16> %a0)
1023 declare i16 @llvm.experimental.vector.reduce.and.i16.v64i16(<64 x i16>)
Dvector-reduce-or.ll642 %1 = call i16 @llvm.experimental.vector.reduce.or.i16.v64i16(<64 x i16> %a0)
1023 declare i16 @llvm.experimental.vector.reduce.or.i16.v64i16(<64 x i16>)
Dvector-reduce-xor.ll642 %1 = call i16 @llvm.experimental.vector.reduce.xor.i16.v64i16(<64 x i16> %a0)
1023 declare i16 @llvm.experimental.vector.reduce.xor.i16.v64i16(<64 x i16>)

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