| /external/llvm/include/llvm/CodeGen/ |
| D | MachineValueType.h | 93 v64i32 = 44, // 64 x i32 enumerator
280 SimpleTy == MVT::v64i32 || SimpleTy == MVT::v32i64); in is2048BitVector()
348 case v64i32: return i32; in getVectorElementType()
383 case v64i32: return 64; in getVectorNumElements()
510 case v64i32: in getSizeInBits()
630 if (NumElements == 64) return MVT::v64i32; in getVectorVT()
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| D | ValueTypes.td | 70 def v64i32 : ValueType<2048,44>; // 32 x i32 vector value
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| /external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/Hexagon/autohvx/ |
| D | ctpop-split.ll | 9 %t0 = call <64 x i16> @llvm.ctpop.v64i32(<64 x i16> %a0)
21 declare <64 x i16> @llvm.ctpop.v64i32(<64 x i16>) #0
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Hexagon/ |
| D | HexagonCallingConv.td | 103 CCIfType<[v64i32,v128i16,v256i8],
109 CCIfType<[v64i32,v128i16,v256i8],
129 CCIfType<[v64i32,v128i16,v256i8],
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| D | HexagonIntrinsicsV60.td | 22 def : Pat < (v32i32 (int_hexagon_V6_lo_128B (v64i32 HvxWR:$src1))),
23 (v32i32 (EXTRACT_SUBREG (v64i32 HvxWR:$src1), vsub_lo)) >;
25 def : Pat < (v32i32 (int_hexagon_V6_hi_128B (v64i32 HvxWR:$src1))),
26 (v32i32 (EXTRACT_SUBREG (v64i32 HvxWR:$src1), vsub_hi)) >;
636 def: Pat<(v64i16 (trunc v64i32:$Vdd)),
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| D | HexagonRegisterInfo.td | 287 [v32i32, v64i32, v32i32]>;
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| D | HexagonISelLoweringHVX.cpp | 20 static const MVT LegalW128[] = { MVT::v256i8, MVT::v128i16, MVT::v64i32 };
50 addRegisterClass(MVT::v64i32, &Hexagon::HvxWRRegClass); in initializeHVXLowering()
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| /external/swiftshader/third_party/llvm-7.0/llvm/include/llvm/Support/ |
| D | MachineValueType.h | 96 v64i32 = 47, // 64 x i32 enumerator
384 SimpleTy == MVT::v64i32 || SimpleTy == MVT::v32i64); in is2048BitVector()
471 case v64i32: in getVectorElementType()
531 case v64i32: return 64; in getVectorNumElements()
748 case v64i32: in getSizeInBits()
871 if (NumElements == 64) return MVT::v64i32; in getVectorVT()
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| /external/llvm/lib/Target/Hexagon/ |
| D | HexagonISelLowering.cpp | 209 if (LocVT == MVT::v32i64 || LocVT == MVT::v64i32 || LocVT == MVT::v128i16 || in CC_Hexagon_VarArg()
360 (LocVT == MVT::v32i64 || LocVT == MVT::v64i32 || LocVT == MVT::v128i16 || in CC_HexagonVector()
425 LocVT == MVT::v64i32 || LocVT == MVT::v32i64) { in RetCC_Hexagon()
426 LocVT = MVT::v64i32; in RetCC_Hexagon()
427 ValVT = MVT::v64i32; in RetCC_Hexagon()
439 if (LocVT == MVT::v16i32 || LocVT == MVT::v32i32 || LocVT == MVT::v64i32) { in RetCC_Hexagon()
497 } else if (LocVT == MVT::v64i32) { in RetCC_HexagonVector()
547 ty == MVT::v32i64 || ty == MVT::v64i32 || ty == MVT::v128i16 || in IsHvxVectorType()
1140 ((RegVT == MVT::v32i64 || RegVT == MVT::v64i32 || in LowerFormalArguments()
1771 addRegisterClass(MVT::v64i32, &Hexagon::VecDblRegs128BRegClass); in HexagonTargetLowering()
[all …]
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| D | HexagonIntrinsicsV60.td | 73 def : Pat < (v32i32 (int_hexagon_V6_lo_128B (v64i32 VecDblRegs128B:$src1))),
74 (v32i32 (EXTRACT_SUBREG (v64i32 VecDblRegs128B:$src1),
78 def : Pat < (v32i32 (int_hexagon_V6_hi_128B (v64i32 VecDblRegs128B:$src1))),
79 (v32i32 (EXTRACT_SUBREG (v64i32 VecDblRegs128B:$src1),
832 def: Pat<(v64i16 (trunc v64i32:$Vdd)),
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| D | HexagonRegisterInfo.td | 238 [v256i8,v128i16,v64i32,v32i64], 2048,
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| D | HexagonInstrInfoV60.td | 800 defm : STrivv_pats <v32i32, v64i32>;
875 defm : LDrivv_pats <v32i32, v64i32>;
1593 def: Pat<(v64i32 (HexagonVCOMBINE (v32i32 VecDblRegs:$Vs),
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/CodeGen/ |
| D | ValueTypes.cpp | 173 case MVT::v64i32: return "v64i32"; in getEVTString()
254 case MVT::v64i32: return VectorType::get(Type::getInt32Ty(Context), 64); in getTypeForEVT()
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| /external/llvm/lib/IR/ |
| D | ValueTypes.cpp | 176 case MVT::v64i32: return "v64i32"; in getEVTString()
254 case MVT::v64i32: return VectorType::get(Type::getInt32Ty(Context), 64); in getTypeForEVT()
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| /external/swiftshader/third_party/llvm-7.0/llvm/include/llvm/CodeGen/ |
| D | ValueTypes.td | 72 def v64i32 : ValueType<2048,47>; // 64 x i32 vector value
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| /external/llvm/utils/TableGen/ |
| D | CodeGenTarget.cpp | 104 case MVT::v64i32: return "MVT::v64i32"; in getEnumName()
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| /external/swiftshader/third_party/llvm-7.0/llvm/utils/TableGen/ |
| D | CodeGenTarget.cpp | 112 case MVT::v64i32: return "MVT::v64i32"; in getEnumName()
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| /external/llvm/include/llvm/IR/ |
| D | Intrinsics.td | 203 def llvm_v64i32_ty : LLVMType<v64i32>; // 64 x i32
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| /external/swiftshader/third_party/llvm-7.0/llvm/include/llvm/IR/ |
| D | Intrinsics.td | 231 def llvm_v64i32_ty : LLVMType<v64i32>; // 64 x i32
|