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Searched refs:v_mul_f16_e32 (Results 1 – 18 of 18) sorted by relevance

/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/AMDGPU/
Dfmul.f16.ll12 ; GFX89: v_mul_f16_e32 v[[R_F16:[0-9]+]], v[[A_F16]], v[[B_F16]]
32 ; GFX89: v_mul_f16_e32 v[[R_F16:[0-9]+]], 0x4200, v[[B_F16]]
51 ; GFX89: v_mul_f16_e32 v[[R_F16:[0-9]+]], 4.0, v[[A_F16]]
81 ; VI-DAG: v_mul_f16_e32 v[[R_F16_LO:[0-9]+]], v[[A_V2_F16]], v[[B_V2_F16]]
116 ; VI-DAG: v_mul_f16_e32 v[[R_F16_0:[0-9]+]], 0x4200, v[[B_V2_F16]]
148 ; VI-DAG: v_mul_f16_e32 v[[R_F16_0:[0-9]+]], 4.0, v[[A_V2_F16]]
179 ; VI: v_mul_f16_e32
181 ; VI: v_mul_f16_e32
208 ; VI-DAG: v_mul_f16_e32 v[[MUL_HI_LO:[0-9]+]], 0x4200, v[[A_HI]]
210 ; VI-DAG: v_mul_f16_e32 v[[MUL_LO_LO:[0-9]+]], 0x4800, v[[A_LO]]
Dllvm.log10.f16.ll18 ; VIGFX9: v_mul_f16_e32 v[[R_F16_0]], 0x34d1, v[[R_F16_0]]
51 ; GFX9: v_mul_f16_e32 v[[R_F32_3:[0-9]+]], v[[R_F16_2]], v[[A_F32_2]]
52 ; VIGFX9: v_mul_f16_e32 v[[R_F32_2:[0-9]+]], v[[R_F16_0]], v[[A_F32_2]]
Dllvm.log.f16.ll18 ; VIGFX9: v_mul_f16_e32 v[[R_F16_0]], 0x398c, v[[R_F16_0]]
51 ; GFX9: v_mul_f16_e32 v[[R_F32_3:[0-9]+]], v[[R_F16_2]], v[[A_F32_2]]
52 ; VIGFX9: v_mul_f16_e32 v[[R_F32_2:[0-9]+]], v[[R_F16_0]], v[[A_F32_2]]
Dfdiv.f16.ll169 ; GFX8_9: v_mul_f16_e32 [[RESULT:v[0-9]+]], [[LHS]], [[RCP]]
191 ; GFX8_9: v_mul_f16_e32 [[RESULT:v[0-9]+]], [[LHS]], [[RCP]]
211 ; GFX8_9: v_mul_f16_e32 [[MUL:v[0-9]+]], 0.5, v{{[0-9]+}}
223 ; GFX8_9: v_mul_f16_e32 [[MUL:v[0-9]+]], 0x2e66, v{{[0-9]+}}
235 ; GFX8_9: v_mul_f16_e32 [[MUL:v[0-9]+]], 0xae66, v{{[0-9]+}}
Dfpext-free.ll123 ; GFX9-F32DENORM-NEXT: v_mul_f16_e32 v2, v2, v3
222 ; GFX9-F32DENORM-NEXT: v_mul_f16_e32 v0, v0, v1
242 ; GFX9-F32DENORM-NEXT: v_mul_f16_e32
305 ; GFX9-F32DENORM-NEXT: v_mul_f16_e32 v3, v3, v4
346 ; GFX9-F32DENORM-NEXT: v_mul_f16_e32 v3, v3, v4
365 ; GFX9-NEXT: v_mul_f16_e32 v3, v3, v4
Dfmul-2-combine-multi-use.ll119 ; VI: v_mul_f16_e32 v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}
204 ; GCN: v_mul_f16_e32 [[RESULT:v[0-9]+]], [[X]], [[TMP0]]
219 ; GCN: v_mul_f16_e32 [[TMP0:v[0-9]+]], [[X:s[0-9]+]], [[K]]
220 ; GCN: v_mul_f16_e32 [[RESULT:v[0-9]+]], [[X]], [[TMP0]]
Dsdwa-peephole.ll155 ; NOSDWA: v_mul_f16_e32 v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}
157 ; SDWA: v_mul_f16_e32 v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}
172 ; NOSDWA: v_mul_f16_e32 v[[DST_MUL:[0-9]+]], v[[DST0]], v[[DST1]]
178 ; VI-DAG: v_mul_f16_e32 v[[DST_MUL_LO:[0-9]+]], v{{[0-9]+}}, v{{[0-9]+}}
195 ; NOSDWA: v_mul_f16_e32 v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}
220 ; NOSDWA: v_mul_f16_e32 v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}
Dfmuladd.f16.ll226 ; VI-DENORM-STRICT: v_mul_f16_e32 [[TMP:v[0-9]+]], [[REGA]], [[REGB]]
256 ; VI-DENORM-STRICT: v_mul_f16_e32 [[TMP:v[0-9]+]], [[REGA]], [[REGB]]
286 ; VI-DENORM-STRICT: v_mul_f16_e32 [[TMP:v[0-9]+]], [[REGA]], [[REGB]]
318 ; VI-DENORM-STRICT: v_mul_f16_e32 [[TMP:v[0-9]+]], [[REGA]], [[REGB]]
351 ; VI-DENORM-STRICT: v_mul_f16_e32 [[TMP:v[0-9]+]], [[REGA]], [[REGB]]
Dfdot2.ll14 ; GFX906: v_mul_f16_e32
15 ; GFX906: v_mul_f16_e32
Dfneg.f16.ll134 ; GFX89-DAG: v_mul_f16_e32 v{{[0-9]+}}, -4.0, [[VAL]]
Dfcanonicalize.ll456 ; GCN: v_mul_f16_e32 {{v[0-9]+}}, 1.0, {{v[0-9]+}}
470 ; GCN-DAG: v_mul_f16_e32 v{{[0-9]+}}, 1.0, v{{[0-9]+}}
Domod.ll224 ; VI: v_mul_f16_e32 v{{[0-9]+}}, 0.5, [[ADD]]{{$}}
Dfcanonicalize.f16.ll76 ; GFX89: v_mul_f16_e32 [[REG:v[0-9]+]], -1.0, v{{[0-9]+}}
/external/swiftshader/third_party/llvm-7.0/llvm/test/MC/AMDGPU/
Dvop2.s416 v_mul_f16_e32 v1, v2, v3 label
/external/llvm/test/MC/Disassembler/AMDGPU/
Dvop2_vi.txt204 # VI: v_mul_f16_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x44]
/external/swiftshader/third_party/llvm-7.0/llvm/test/MC/Disassembler/AMDGPU/
Dvop2_vi.txt204 # VI: v_mul_f16_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x44]
Dgfx8_dasm_all.txt37017 # CHECK: v_mul_f16_e32 v5, v1, v2 ; encoding: [0x01,0x05,0x0a,0x44]
37020 # CHECK: v_mul_f16_e32 v255, v1, v2 ; encoding: [0x01,0x05,0xfe,0x45]
37023 # CHECK: v_mul_f16_e32 v5, v255, v2 ; encoding: [0xff,0x05,0x0a,0x44]
37026 # CHECK: v_mul_f16_e32 v5, s1, v2 ; encoding: [0x01,0x04,0x0a,0x44]
37029 # CHECK: v_mul_f16_e32 v5, s101, v2 ; encoding: [0x65,0x04,0x0a,0x44]
37032 # CHECK: v_mul_f16_e32 v5, flat_scratch_lo, v2 ; encoding: [0x66,0x04,0x0a,0x44]
37035 # CHECK: v_mul_f16_e32 v5, flat_scratch_hi, v2 ; encoding: [0x67,0x04,0x0a,0x44]
37038 # CHECK: v_mul_f16_e32 v5, vcc_lo, v2 ; encoding: [0x6a,0x04,0x0a,0x44]
37041 # CHECK: v_mul_f16_e32 v5, vcc_hi, v2 ; encoding: [0x6b,0x04,0x0a,0x44]
37044 # CHECK: v_mul_f16_e32 v5, tba_lo, v2 ; encoding: [0x6c,0x04,0x0a,0x44]
[all …]
Dgfx9_dasm_all.txt31668 # CHECK: v_mul_f16_e32 v5, v1, v2 ; encoding: [0x01,0x05,0x0a,0x44]
31671 # CHECK: v_mul_f16_e32 v255, v1, v2 ; encoding: [0x01,0x05,0xfe,0x45]
31674 # CHECK: v_mul_f16_e32 v5, v255, v2 ; encoding: [0xff,0x05,0x0a,0x44]
31677 # CHECK: v_mul_f16_e32 v5, s1, v2 ; encoding: [0x01,0x04,0x0a,0x44]
31680 # CHECK: v_mul_f16_e32 v5, s101, v2 ; encoding: [0x65,0x04,0x0a,0x44]
31683 # CHECK: v_mul_f16_e32 v5, flat_scratch_lo, v2 ; encoding: [0x66,0x04,0x0a,0x44]
31686 # CHECK: v_mul_f16_e32 v5, flat_scratch_hi, v2 ; encoding: [0x67,0x04,0x0a,0x44]
31689 # CHECK: v_mul_f16_e32 v5, vcc_lo, v2 ; encoding: [0x6a,0x04,0x0a,0x44]
31692 # CHECK: v_mul_f16_e32 v5, vcc_hi, v2 ; encoding: [0x6b,0x04,0x0a,0x44]
31695 # CHECK: v_mul_f16_e32 v5, m0, v2 ; encoding: [0x7c,0x04,0x0a,0x44]
[all …]