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/external/swiftshader/third_party/llvm-7.0/llvm/test/MC/AMDGPU/
Dvopc-vi.s5 v_cmp_class_f16 vcc, v2, v4
9 v_cmpx_class_f16 vcc, v2, v4
13 v_cmp_f_f16 vcc, v2, v4
17 v_cmp_lt_f16 vcc, v2, v4
21 v_cmp_eq_f16 vcc, v2, v4
25 v_cmp_le_f16 vcc, v2, v4
29 v_cmp_gt_f16 vcc, v2, v4
33 v_cmp_lg_f16 vcc, v2, v4
37 v_cmp_ge_f16 vcc, v2, v4
41 v_cmp_o_f16 vcc, v2, v4
[all …]
Dgfx7_asm_all.s9795 s_load_dword s5, vcc, s2
9855 s_load_dwordx2 vcc, s[2:3], s2
9867 s_load_dwordx2 s[10:11], vcc, s2
9936 s_load_dwordx4 s[20:23], vcc, s2
10005 s_load_dwordx8 s[20:27], vcc, s2
10074 s_load_dwordx16 s[20:35], vcc, s2
10194 s_buffer_load_dwordx2 vcc, s[4:7], s2
10428 s_memtime vcc
10545 s_mov_b64 vcc, s[2:3]
10569 s_mov_b64 s[10:11], vcc
[all …]
Dgfx8_asm_all.s10047 s_load_dword s5, vcc, s2
10110 s_load_dwordx2 vcc, s[2:3], s2
10131 s_load_dwordx2 s[10:11], vcc, s2
10203 s_load_dwordx4 s[20:23], vcc, s2
10275 s_load_dwordx8 s[20:27], vcc, s2
10344 s_load_dwordx16 s[20:35], vcc, s2
10488 s_buffer_load_dwordx2 vcc, s[4:7], s2
10767 s_store_dword s1, vcc, m0
10797 s_store_dwordx2 vcc, s[4:5], m0
10818 s_store_dwordx2 s[2:3], vcc, m0
[all …]
Dvop-err.s96 v_cndmask_b32 v0, s1, v2, vcc
99 v_cndmask_b32 v0, flat_scratch_lo, v2, vcc
102 v_cndmask_b32 v0, flat_scratch_hi, v2, vcc
105 v_cndmask_b32 v0, exec_lo, v2, vcc
108 v_cndmask_b32 v0, exec_hi, v2, vcc
114 v_cndmask_b32_e64 v0, s1, v2, vcc
117 v_cndmask_b32_e64 v0, flat_scratch_lo, v2, vcc
120 v_cndmask_b32_e64 v0, flat_scratch_hi, v2, vcc
156 v_addc_u32 v0, vcc, s0, v0, vcc
159 v_addc_u32 v0, vcc, flat_scratch_lo, v0, vcc
[all …]
Dvop2.s99 v_add_i32_e32 v0, vcc, 0.5, v0
103 v_add_i32_e32 v0, vcc, 3.125, v0
110 v_cndmask_b32 v1, v2, v3, vcc
113 v_cndmask_b32_e32 v1, v2, v3, vcc
275 v_add_i32_e32 v1, vcc, v2, v3
287 v_add_i32_e64 v1, vcc, v2, v3
291 v_add_u32 v1, vcc, v2, v3
299 v_sub_i32 v1, vcc, v2, v3
307 v_sub_u32 v1, vcc, v2, v3
315 v_subrev_i32 v1, vcc, v2, v3
[all …]
Dvopc.s10 v_cmp_lt_f32 vcc, s2, v4
15 v_cmp_lt_f32 vcc, 0, v4
20 v_cmp_lt_f32 vcc, 10.0, v4
25 v_cmp_lt_f32 vcc, v255, v255
30 v_cmp_lt_f32_e32 vcc, v2, v4
39 v_cmp_f_f32 vcc, v2, v4
43 v_cmp_lt_f32 vcc, v2, v4
50 v_cmp_f_f64 vcc, v[2:3], v[4:5]
57 v_cmp_f_i32 vcc, v2, v4
63 v_cmp_f_i64 vcc, v[2:3], v[4:5]
Dgfx9_asm_all.s10756 s_load_dword s5, vcc, s0
10795 s_load_dwordx2 vcc, s[2:3], s0
10807 s_load_dwordx2 s[10:11], vcc, s0
10852 s_load_dwordx4 s[20:23], vcc, s0
10897 s_load_dwordx8 s[20:27], vcc, s0
10942 s_load_dwordx16 s[20:35], vcc, s0
11029 s_buffer_load_dwordx2 vcc, s[4:7], s0
11206 s_store_dword s1, vcc, s0
11245 s_store_dwordx2 vcc, s[4:5], s0
11257 s_store_dwordx2 s[2:3], vcc, s0
[all …]
Dvop_sdwa.s117 v_cmp_class_f32_sdwa vcc, -v1, sext(v2) src0_sel:BYTE_2 src1_sel:WORD_0
527 v_add_u32_sdwa v1, vcc, v2, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:BYTE_2
532 v_sub_u32_sdwa v1, vcc, v2, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:BYTE_2
537 v_subrev_u32_sdwa v1, vcc, v2, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:BYTE…
542 v_addc_u32_sdwa v1, vcc, v2, v3, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:B…
547 v_subb_u32_sdwa v1, vcc, v2, v3, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:B…
552 v_subbrev_u32_sdwa v1, vcc, v2, v3, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_se…
557 v_add_co_u32_sdwa v1, vcc, v2, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:BYTE…
562 v_sub_co_u32_sdwa v1, vcc, v2, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:BYTE…
567 v_subrev_co_u32_sdwa v1, vcc, v2, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:B…
[all …]
/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/AMDGPU/
Dreduce-saveexec.mir5 # GCN: $exec = S_AND_B64 $exec, killed $vcc
11 $vcc = IMPLICIT_DEF
12 $sgpr0_sgpr1 = S_AND_B64 $exec, killed $vcc, implicit-def $scc
18 # GCN: $exec = S_AND_B64 killed $vcc, $exec
24 $vcc = IMPLICIT_DEF
25 $sgpr0_sgpr1 = S_AND_B64 killed $vcc, $exec, implicit-def $scc
31 # GCN: $sgpr0_sgpr1 = S_AND_B64 $exec, killed $vcc
37 $vcc = IMPLICIT_DEF
38 $sgpr0_sgpr1 = S_AND_B64 $exec, killed $vcc, implicit-def $scc
44 # GCN: $sgpr0_sgpr1 = S_AND_SAVEEXEC_B64 $vcc
[all …]
Dendpgm-dce.mir16 $vcc = IMPLICIT_DEF
19 $sgpr0_sgpr1 = S_OR_B64 $exec, killed $vcc, implicit-def $scc
27 # GCN: $sgpr0_sgpr1 = S_OR_B64 $exec, killed $vcc, implicit-def $scc
40 $vcc = IMPLICIT_DEF
43 $sgpr0_sgpr1 = S_OR_B64 $exec, killed $vcc, implicit-def $scc
51 # GCN: $sgpr0_sgpr1 = S_OR_B64 $exec, killed $vcc, implicit-def $scc
64 $vcc = IMPLICIT_DEF
67 $sgpr0_sgpr1 = S_OR_B64 $exec, killed $vcc, implicit-def $scc
75 # GCN: $sgpr0_sgpr1 = S_OR_B64 $exec, killed $vcc, implicit-def $scc
85 $vcc = IMPLICIT_DEF
[all …]
Dselect-opt.ll8 ; GCN-DAG: v_cmp_ne_u32_e32 vcc,
10 ; GCN: s_and_b64 vcc, vcc, [[CMP1]]
11 ; GCN: v_cndmask_b32_e32 [[RESULT:v[0-9]+]], {{v[0-9]+}}, {{v[0-9]+}}, vcc
24 ; GCN-DAG: v_cmp_lg_f32_e32 vcc
26 ; GCN: s_and_b64 vcc, vcc, [[CMP1]]
27 ; GCN: v_cndmask_b32_e32 [[RESULT:v[0-9]+]], {{v[0-9]+}}, {{v[0-9]+}}, vcc
40 ; GCN-DAG: v_cmp_ne_u32_e32 vcc,
42 ; GCN: s_and_b64 vcc, vcc, [[CMP1]]
43 ; GCN: v_cndmask_b32_e32 v[[RESULT1:[0-9]+]], {{v[0-9]+}}, {{v[0-9]+}}, vcc
44 ; GCN: v_cndmask_b32_e32 v[[RESULT0:[0-9]+]], {{v[0-9]+}}, {{v[0-9]+}}, vcc
[all …]
Dsdwa-peephole-instr.mir328 # GFX89: $vcc = V_CMP_EQ_F32_sdwa 0, %{{[0-9]+}}, 0, %{{[0-9]+}}, 0, 6, 4, implicit-def $vcc, impli…
329 # GFX89: $vcc = V_CMPX_GT_F32_sdwa 0, %{{[0-9]+}}, 0, %{{[0-9]+}}, 0, 6, 4, implicit-def $vcc, impl…
330 # GFX89: $vcc = V_CMP_LT_I32_sdwa 0, %{{[0-9]+}}, 0, %{{[0-9]+}}, 0, 6, 4, implicit-def $vcc, impli…
331 # GFX89: $vcc = V_CMPX_EQ_I32_sdwa 0, %{{[0-9]+}}, 0, %{{[0-9]+}}, 0, 6, 4, implicit-def $vcc, impl…
334 # VI: $vcc = V_CMP_EQ_F32_sdwa 0, %{{[0-9]+}}, 0, %{{[0-9]+}}, 0, 6, 4, implicit-def $vcc, implicit…
336 # VI: $vcc = V_CMP_LT_I32_sdwa 0, %{{[0-9]+}}, 0, %3, 0, 6, 4, implicit-def $vcc, implicit $exec
339 # GFX9: $vcc = V_CMP_EQ_F32_sdwa 0, %{{[0-9]+}}, 0, %{{[0-9]+}}, 0, 6, 4, implicit-def $vcc, implic…
341 … V_CMPX_GT_F32_sdwa 0, %{{[0-9]+}}, 0, %{{[0-9]+}}, 0, 6, 4, implicit-def $vcc, implicit-def $exec…
342 # GFX9: $vcc = V_CMP_LT_I32_sdwa 0, %{{[0-9]+}}, 0, %{{[0-9]+}}, 0, 6, 4, implicit-def $vcc, implic…
344 … V_CMPX_EQ_I32_sdwa 0, %{{[0-9]+}}, 0, %{{[0-9]+}}, 0, 6, 4, implicit-def $vcc, implicit-def $exec…
[all …]
Dsub.ll30 ; SI: v_subrev_i32_e32 v{{[0-9]+, vcc, v[0-9]+, v[0-9]+}}
44 ; SI: v_sub_i32_e32 v{{[0-9]+}}, vcc, 0x7b, v{{[0-9]+}}
57 ; SI: v_sub_i32_e32 v{{[0-9]+, vcc, v[0-9]+, v[0-9]+}}
58 ; SI: v_sub_i32_e32 v{{[0-9]+, vcc, v[0-9]+, v[0-9]+}}
77 ; SI: v_sub_i32_e32 v{{[0-9]+, vcc, v[0-9]+, v[0-9]+}}
78 ; SI: v_sub_i32_e32 v{{[0-9]+, vcc, v[0-9]+, v[0-9]+}}
79 ; SI: v_sub_i32_e32 v{{[0-9]+, vcc, v[0-9]+, v[0-9]+}}
80 ; SI: v_sub_i32_e32 v{{[0-9]+, vcc, v[0-9]+, v[0-9]+}}
96 ; SI: v_subrev_i32_e32 v{{[0-9]+}}, vcc,
186 ; SI: v_sub_i32_e32 v{{[0-9]+}}, vcc,
[all …]
Dfcmp.f16.ll9 ; SI: v_cmp_lt_f32_e32 vcc, v[[A_F32]], v[[B_F32]]
10 ; VI: v_cmp_lt_f16_e32 vcc, v[[A_F16]], v[[B_F16]]
34 ; SI: v_cmp_lt_f32_e32 vcc, v[[A_F32]], v[[B_F32]]
60 ; SI: v_cmp_eq_f32_e32 vcc, v[[A_F32]], v[[B_F32]]
61 ; VI: v_cmp_eq_f16_e32 vcc, v[[A_F16]], v[[B_F16]]
83 ; SI: v_cmp_le_f32_e32 vcc, v[[A_F32]], v[[B_F32]]
84 ; VI: v_cmp_le_f16_e32 vcc, v[[A_F16]], v[[B_F16]]
106 ; SI: v_cmp_gt_f32_e32 vcc, v[[A_F32]], v[[B_F32]]
107 ; VI: v_cmp_gt_f16_e32 vcc, v[[A_F16]], v[[B_F16]]
129 ; SI: v_cmp_lg_f32_e32 vcc, v[[A_F32]], v[[B_F32]]
[all …]
Dwaitcnt-back-edge-loop.mir32 V_CMP_NE_U32_e32 0, $vgpr5, implicit-def $vcc, implicit $exec
33 $vcc = S_AND_B64 $exec, killed $vcc, implicit-def dead $scc
34 S_CBRANCH_VCCZ %bb.5, implicit killed $vcc
39 V_CMP_EQ_U32_e32 9, killed $vgpr5, implicit-def $vcc, implicit $exec
40 $vcc = S_AND_B64 $exec, killed $vcc, implicit-def dead $scc
41 S_CBRANCH_VCCZ %bb.3, implicit killed $vcc
48 V_CMP_EQ_U32_e32 2, killed $vgpr4, implicit-def $vcc, implicit $exec
49 $vcc = S_AND_B64 $exec, killed $vcc, implicit-def dead $scc
51 S_CBRANCH_VCCZ %bb.1, implicit killed $vcc
76 S_CBRANCH_VCCZ %bb.1, implicit $vcc
[all …]
Dfdiv32-to-rcp-folding.ll8 ; GCN-DENORM-DAG: v_cmp_gt_f32_e64 vcc, |[[VAL]]|, [[L]]
9 ; GCN-DENORM-DAG: v_cndmask_b32_e32 [[SCALE:v[0-9]+]], 1.0, [[S]], vcc
28 ; GCN-DENORM-DAG: v_cmp_gt_f32_e64 vcc, |[[VAL]]|, [[L]]
29 ; GCN-DENORM-DAG: v_cndmask_b32_e32 [[SCALE:v[0-9]+]], 1.0, [[S]], vcc
48 ; GCN-DENORM-DAG: v_cmp_gt_f32_e64 vcc, |[[VAL]]|, [[L]]
49 ; GCN-DENORM-DAG: v_cndmask_b32_e32 [[SCALE:v[0-9]+]], 1.0, [[S]], vcc
69 ; GCN-DENORM-DAG: v_cmp_gt_f32_e64 vcc, |[[VAL]]|, [[L]]
70 ; GCN-DENORM-DAG: v_cndmask_b32_e32 [[SCALE:v[0-9]+]], 1.0, [[S]], vcc
90 ; GCN-DENORM-DAG: v_cmp_gt_f32_e64 vcc, |s{{[0-9]+}}|, [[L]]
91 ; GCN-DENORM-DAG: v_cndmask_b32_e32 v{{[0-9]+}}, 1.0, [[S]], vcc
[all …]
Dv_cndmask.ll7 ; GCN: v_cmp_eq_u32_e64 [[COND:vcc|s\[[0-9]+:[0-9]+\]]], s{{[0-9]+}}, 0
28 ; GCN: v_cmp_eq_u32_e64 vcc, s{{[0-9]+}}, 0
29 ; GCN: v_cndmask_b32_e32 v{{[0-9]}}, -1, v{{[0-9]}}, vcc
47 ; GCN-DAG: v_cmp_nlg_f32_e64 vcc, s[[X]], 0
49 ; GCN: v_cndmask_b32_e32 v{{[0-9]+}}, 1.0, [[VZ]], vcc
62 ; GCN-DAG: v_cmp_nlg_f32_e64 vcc, [[X]], 0
64 ; GCN: v_cndmask_b32_e32 v{{[0-9]+}}, 1.0, [[VX]], vcc
77 ; GCN-DAG: v_cmp_nlg_f32_e64 vcc, s[[X]], 0
79 ; GCN: v_cndmask_b32_e32 v{{[0-9]+}}, 0, [[VZ]], vcc
92 ; GCN-DAG: v_cmp_nlg_f32_e64 vcc, [[X]], 0
[all …]
Dflat-load-clustering.mir61 undef %12.sub0 = V_ADD_I32_e32 %4.sub0, %7, implicit-def $vcc, implicit $exec
63 %12.sub1 = V_ADDC_U32_e32 %11, %2, implicit-def dead $vcc, implicit killed $vcc, implicit $exec
65 undef %9.sub0 = V_ADD_I32_e32 %3.sub0, %7, implicit-def $vcc, implicit $exec
67 %9.sub1 = V_ADDC_U32_e32 %8, %2, implicit-def dead $vcc, implicit killed $vcc, implicit $exec
68 undef %13.sub0 = V_ADD_I32_e32 16, %12.sub0, implicit-def $vcc, implicit $exec
69 …%13.sub1 = V_ADDC_U32_e32 %12.sub1, %2, implicit-def dead $vcc, implicit killed $vcc, implicit $ex…
71 undef %10.sub0 = V_ADD_I32_e32 16, %9.sub0, implicit-def $vcc, implicit $exec
72 …%10.sub1 = V_ADDC_U32_e32 %9.sub1, %2, implicit-def dead $vcc, implicit killed $vcc, implicit $exec
Dearly-if-convert-cost.ll8 ; GCN: v_cmp_neq_f64_e32 vcc, 1.0, v{{\[}}[[VAL_LO]]:[[VAL_HI]]{{\]}}
10 ; GCN-DAG: v_cndmask_b32_e32 v[[RESULT_LO:[0-9]+]], v[[ADD_LO]], v[[VAL_LO]], vcc
11 ; GCN-DAG: v_cndmask_b32_e32 v[[RESULT_HI:[0-9]+]], v[[ADD_HI]], v[[VAL_HI]], vcc
29 ; vcc branch with SGPR inputs
57 ; GCN: s_mov_b64 vcc, [[CMP]]
59 ; GCN: v_cndmask_b32_e32 v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}, vcc
60 ; GCN: v_cndmask_b32_e32 v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}, vcc
61 ; GCN: v_cndmask_b32_e32 v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}, vcc
88 ; GCN: s_mov_b64 vcc, [[CMP]]
90 ; GCN: v_cndmask_b32_e32 v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}, vcc
[all …]
/external/llvm/test/MC/AMDGPU/
Dvop2.s99 v_add_i32 v0, vcc, 0.5, v0
103 v_add_i32 v0, vcc, 3.125, v0
110 v_cndmask_b32 v1, v2, v3, vcc
113 v_cndmask_b32_e32 v1, v2, v3, vcc
267 v_add_i32 v1, vcc, v2, v3
279 v_add_i32_e64 v1, vcc, v2, v3
283 v_add_u32 v1, vcc, v2, v3
291 v_sub_i32 v1, vcc, v2, v3
299 v_sub_u32 v1, vcc, v2, v3
307 v_subrev_i32 v1, vcc, v2, v3
[all …]
Dvopc.s10 v_cmp_lt_f32 vcc, s2, v4
15 v_cmp_lt_f32 vcc, 0, v4
20 v_cmp_lt_f32 vcc, 10.0, v4
25 v_cmp_lt_f32 vcc, v255, v255
30 v_cmp_lt_f32_e32 vcc, v2, v4
39 v_cmp_f_f32 vcc, v2, v4
43 v_cmp_lt_f32 vcc, v2, v4
50 v_cmp_f_f64 vcc, v[2:3], v[4:5]
57 v_cmp_f_i32 vcc, v2, v4
63 v_cmp_f_i64 vcc, v[2:3], v[4:5]
/external/llvm/test/MC/Disassembler/AMDGPU/
Dvopc_vi.txt3 # VI: v_cmp_lt_f32_e32 vcc, s2, v4 ; encoding: [0x02,0x08,0x82,0x7c]
6 # VI: v_cmp_lt_f32_e32 vcc, 0, v4 ; encoding: [0x80,0x08,0x82,0x7c]
9 # VI: v_cmp_lt_f32_e32 vcc, 0x41200000, v4 ; encoding: [0xff,0x08,0x82,0x7c,0x00,0x00,0x20,0x41]
12 # VI: v_cmp_lt_f32_e32 vcc, v255, v255 ; encoding: [0xff,0xff,0x83,0x7c]
15 # VI: v_cmp_lt_f32_e32 vcc, v2, v4 ; encoding: [0x02,0x09,0x82,0x7c]
18 # VI: v_cmp_f_f32_e32 vcc, v2, v4 ; encoding: [0x02,0x09,0x80,0x7c]
21 # VI: v_cmp_lt_f32_e32 vcc, v2, v4 ; encoding: [0x02,0x09,0x82,0x7c]
24 # VI: v_cmp_f_f64_e32 vcc, v[2:3], v[4:5] ; encoding: [0x02,0x09,0xc0,0x7c]
27 # VI: v_cmp_f_i32_e32 vcc, v2, v4 ; encoding: [0x02,0x09,0x80,0x7d]
30 # VI: v_cmp_f_i64_e32 vcc, v[2:3], v[4:5] ; encoding: [0x02,0x09,0xc0,0x7d]
/external/swiftshader/third_party/llvm-7.0/llvm/test/MC/Disassembler/AMDGPU/
Dvopc_vi.txt3 # VI: v_cmp_lt_f32_e32 vcc, s2, v4 ; encoding: [0x02,0x08,0x82,0x7c]
6 # VI: v_cmp_lt_f32_e32 vcc, 0, v4 ; encoding: [0x80,0x08,0x82,0x7c]
9 # VI: v_cmp_lt_f32_e32 vcc, 0x41200000, v4 ; encoding: [0xff,0x08,0x82,0x7c,0x00,0x00,0x20,0x41]
12 # VI: v_cmp_lt_f32_e32 vcc, v255, v255 ; encoding: [0xff,0xff,0x83,0x7c]
15 # VI: v_cmp_lt_f32_e32 vcc, v2, v4 ; encoding: [0x02,0x09,0x82,0x7c]
18 # VI: v_cmp_f_f32_e32 vcc, v2, v4 ; encoding: [0x02,0x09,0x80,0x7c]
21 # VI: v_cmp_lt_f32_e32 vcc, v2, v4 ; encoding: [0x02,0x09,0x82,0x7c]
24 # VI: v_cmp_f_f64_e32 vcc, v[2:3], v[4:5] ; encoding: [0x02,0x09,0xc0,0x7c]
27 # VI: v_cmp_f_i32_e32 vcc, v2, v4 ; encoding: [0x02,0x09,0x80,0x7d]
30 # VI: v_cmp_f_i64_e32 vcc, v[2:3], v[4:5] ; encoding: [0x02,0x09,0xc0,0x7d]
/external/llvm/test/Object/AMDGPU/
Dobjdump.s14 v_add_i32_e32 v1, vcc, s0, v1
16 v_cmp_ge_i32_e32 vcc, s0, v0
17 s_and_saveexec_b64 s[0:1], vcc
30 s_and_saveexec_b64 s[0:1], vcc
36 v_add_i32_e32 v10, vcc, s8, v10
38 v_addc_u32_e32 v11, vcc, v6, v11, vcc
/external/swiftshader/third_party/llvm-7.0/llvm/test/Object/AMDGPU/
Dobjdump.s15 v_add_u32_e32 v1, vcc, s0, v1
18 v_cmp_ge_i32_e32 vcc, s0, v0
19 s_and_saveexec_b64 s[0:1], vcc
33 s_and_saveexec_b64 s[0:1], vcc
40 v_add_u32_e32 v10, vcc, s8, v10
42 v_addc_u32_e32 v11, vcc, v6, v11, vcc

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