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1# RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs -run-pass machine-scheduler -o - %s | FileCheck -check-prefix=GCN %s
2
3# CGN-LABEL: name: flat_load_clustering
4# GCN:      FLAT_LOAD_DWORD
5# GCN-NEXT: FLAT_LOAD_DWORD
6--- |
7  define amdgpu_kernel void @flat_load_clustering(i32 addrspace(1)* nocapture %arg, i32 addrspace(2)* nocapture readonly %arg1) {
8  bb:
9    %tid = tail call i32 @llvm.amdgcn.workitem.id.x()
10    %idxprom = sext i32 %tid to i64
11    %gep1 = getelementptr inbounds i32, i32 addrspace(2)* %arg1, i64 %idxprom
12    %load1 = load i32, i32 addrspace(2)* %gep1, align 4
13    %gep2 = getelementptr inbounds i32, i32 addrspace(1)* %arg, i64 %idxprom
14    %gep34 = getelementptr inbounds i32, i32 addrspace(2)* %gep1, i64 4
15    %load2 = load i32, i32 addrspace(2)* %gep34, align 4
16    %gep4 = getelementptr inbounds i32, i32 addrspace(1)* %gep2, i64 4
17    store i32 %load1, i32 addrspace(1)* %gep2, align 4
18    store i32 %load2, i32 addrspace(1)* %gep4, align 4
19    ret void
20  }
21
22  declare i32 @llvm.amdgcn.workitem.id.x()
23
24...
25---
26name:            flat_load_clustering
27alignment:       0
28exposesReturnsTwice: false
29legalized:       false
30regBankSelected: false
31selected:        false
32tracksRegLiveness: true
33registers:
34  - { id: 0, class: vgpr_32 }
35  - { id: 1, class: sgpr_64 }
36  - { id: 2, class: vgpr_32 }
37  - { id: 3, class: sreg_64_xexec }
38  - { id: 4, class: sreg_64_xexec }
39  - { id: 5, class: vgpr_32 }
40  - { id: 6, class: vgpr_32 }
41  - { id: 7, class: vgpr_32 }
42  - { id: 8, class: vgpr_32 }
43  - { id: 9, class: vreg_64 }
44  - { id: 10, class: vreg_64 }
45  - { id: 11, class: vgpr_32 }
46  - { id: 12, class: vreg_64 }
47  - { id: 13, class: vreg_64 }
48liveins:
49  - { reg: '$vgpr0', virtual-reg: '%0' }
50  - { reg: '$sgpr4_sgpr5', virtual-reg: '%1' }
51body:             |
52  bb.0.bb:
53    liveins: $vgpr0, $sgpr4_sgpr5
54
55    %1 = COPY $sgpr4_sgpr5
56    %0 = COPY $vgpr0
57    %3 = S_LOAD_DWORDX2_IMM %1, 0, 0 :: (non-temporal dereferenceable invariant load 8 from `i64 addrspace(2)* undef`)
58    %4 = S_LOAD_DWORDX2_IMM %1, 8, 0 :: (non-temporal dereferenceable invariant load 8 from `i64 addrspace(2)* undef`)
59    %7 = V_LSHLREV_B32_e32 2, %0, implicit $exec
60    %2 = V_MOV_B32_e32 0, implicit $exec
61    undef %12.sub0 = V_ADD_I32_e32 %4.sub0, %7, implicit-def $vcc, implicit $exec
62    %11 = COPY %4.sub1
63    %12.sub1 = V_ADDC_U32_e32 %11, %2, implicit-def dead $vcc, implicit killed $vcc, implicit $exec
64    %5 = FLAT_LOAD_DWORD %12, 0, 0, 0, implicit $exec, implicit $flat_scr :: (load 4 from %ir.gep1)
65    undef %9.sub0 = V_ADD_I32_e32 %3.sub0, %7, implicit-def $vcc, implicit $exec
66    %8 = COPY %3.sub1
67    %9.sub1 = V_ADDC_U32_e32 %8, %2, implicit-def dead $vcc, implicit killed $vcc, implicit $exec
68    undef %13.sub0 = V_ADD_I32_e32 16, %12.sub0, implicit-def $vcc, implicit $exec
69    %13.sub1 = V_ADDC_U32_e32 %12.sub1, %2, implicit-def dead $vcc, implicit killed $vcc, implicit $exec
70    %6 = FLAT_LOAD_DWORD %13, 0, 0, 0, implicit $exec, implicit $flat_scr :: (load 4 from %ir.gep34)
71    undef %10.sub0 = V_ADD_I32_e32 16, %9.sub0, implicit-def $vcc, implicit $exec
72    %10.sub1 = V_ADDC_U32_e32 %9.sub1, %2, implicit-def dead $vcc, implicit killed $vcc, implicit $exec
73    FLAT_STORE_DWORD %9, %5, 0, 0, 0, implicit $exec, implicit $flat_scr :: (store 4 into %ir.gep2)
74    FLAT_STORE_DWORD %10, %6, 0, 0, 0, implicit $exec, implicit $flat_scr :: (store 4 into %ir.gep4)
75    S_ENDPGM
76
77...
78