| /external/mesa3d/src/intel/compiler/ |
| D | brw_vec4.h | 158 bool is_dep_ctrl_unsafe(const vec4_instruction *inst);
164 bool is_supported_64bit_region(vec4_instruction *inst, unsigned arg);
169 vec4_instruction *inst, int arg);
171 vec4_instruction *emit(vec4_instruction *inst);
173 vec4_instruction *emit(enum opcode opcode);
174 vec4_instruction *emit(enum opcode opcode, const dst_reg &dst);
175 vec4_instruction *emit(enum opcode opcode, const dst_reg &dst,
177 vec4_instruction *emit(enum opcode opcode, const dst_reg &dst,
179 vec4_instruction *emit(enum opcode opcode, const dst_reg &dst,
183 vec4_instruction *emit_before(bblock_t *block,
[all …]
|
| D | brw_vec4_visitor.cpp | 30 vec4_instruction::vec4_instruction(enum opcode opcode, const dst_reg &dst, in vec4_instruction() function in brw::vec4_instruction
64 vec4_instruction *
65 vec4_visitor::emit(vec4_instruction *inst) in emit()
75 vec4_instruction *
76 vec4_visitor::emit_before(bblock_t *block, vec4_instruction *inst, in emit_before()
77 vec4_instruction *new_inst) in emit_before()
87 vec4_instruction *
91 return emit(new(mem_ctx) vec4_instruction(opcode, dst, src0, src1, src2)); in emit()
95 vec4_instruction *
99 return emit(new(mem_ctx) vec4_instruction(opcode, dst, src0, src1)); in emit()
[all …]
|
| D | brw_ir_vec4.h | 268 class vec4_instruction : public backend_instruction {
270 DECLARE_RALLOC_CXX_OPERATORS(vec4_instruction)
272 vec4_instruction(enum opcode opcode,
366 inline vec4_instruction *
368 vec4_instruction *inst) in set_predicate_inv()
378 inline vec4_instruction *
379 set_predicate(enum brw_predicate pred, vec4_instruction *inst) in set_predicate()
388 inline vec4_instruction *
389 set_condmod(enum brw_conditional_mod mod, vec4_instruction *inst) in set_condmod()
399 inline vec4_instruction *
[all …]
|
| D | brw_vec4_cse.cpp | 41 vec4_instruction *generator;
49 is_expression(const vec4_instruction *const inst) in is_expression()
98 operands_match(const vec4_instruction *a, const vec4_instruction *b) in operands_match()
116 instructions_match(vec4_instruction *a, vec4_instruction *b) in instructions_match()
147 foreach_inst_in_block (vec4_instruction, inst, block) { in opt_cse_local()
191 vec4_instruction *copy = in opt_cse_local()
212 vec4_instruction *copy = in opt_cse_local()
226 vec4_instruction *prev = (vec4_instruction *)inst->prev; in opt_cse_local()
|
| D | brw_vec4.cpp | 150 vec4_instruction::is_send_from_grf() in is_send_from_grf()
191 vec4_instruction::has_source_and_destination_hazard() const in has_source_and_destination_hazard()
210 vec4_instruction::size_read(unsigned arg) const in size_read()
245 vec4_instruction::can_do_source_mods(const struct gen_device_info *devinfo) in can_do_source_mods()
260 vec4_instruction::can_do_writemask(const struct gen_device_info *devinfo) in can_do_writemask()
297 vec4_instruction::can_change_types() const in can_change_types()
316 vec4_visitor::implied_mrf_writes(vec4_instruction *inst) in implied_mrf_writes()
389 vec4_instruction *imm_inst[4]; in opt_vector_float()
393 foreach_inst_in_block_safe(vec4_instruction, inst, block) { in opt_vector_float()
432 vec4_instruction *mov = MOV(imm_inst[0]->dst, brw_imm_vf(vf)); in opt_vector_float()
[all …]
|
| D | brw_vec4_reg_allocate.cpp | 55 foreach_block_and_inst(block, vec4_instruction, inst, cfg) { in reg_allocate_trivial()
75 foreach_block_and_inst(block, vec4_instruction, inst, cfg) { in reg_allocate_trivial()
227 foreach_block_and_inst(block, vec4_instruction, inst, cfg) { in reg_allocate()
269 foreach_block_and_inst(block, vec4_instruction, inst, cfg) { in reg_allocate()
303 can_use_scratch_for_source(const vec4_instruction *inst, unsigned i, in can_use_scratch_for_source()
316 for (vec4_instruction *prev_inst = (vec4_instruction *) inst->prev; in can_use_scratch_for_source()
318 prev_inst = (vec4_instruction *) prev_inst->prev) { in can_use_scratch_for_source()
399 foreach_block_and_inst(block, vec4_instruction, inst, cfg) { in evaluate_spill_costs()
513 foreach_block_and_inst(block, vec4_instruction, inst, cfg) { in spill_reg()
|
| D | test_vec4_register_coalesce.cpp | 85 virtual vec4_instruction *emit_urb_write_opcode(bool complete) in emit_urb_write_opcode()
137 vec4_instruction *mul = v->emit(v->MUL(temp, something, brw_imm_f(1.0f))); in TEST_F()
161 vec4_instruction *mul = v->emit(v->MUL(temp, something, brw_imm_f(1.0f))); in TEST_F()
184 vec4_instruction *dp4 = v->emit(v->DP4(temp, some_src_1, some_src_2)); in TEST_F()
202 vec4_instruction *dp4 = v->emit(v->DP4(temp, some_src_1, some_src_2)); in TEST_F()
228 vec4_instruction *mul = v->emit(v->MUL(temp, some_src_1, some_src_2)); in TEST_F()
|
| D | brw_vec4_gs_visitor.cpp | 100 foreach_block_and_inst(block, vec4_instruction, inst, cfg) { in setup_varying_inputs()
168 vec4_instruction *inst = emit(GS_OPCODE_SET_DWORD_2, r0, brw_imm_ud(0u)); in emit_prolog()
226 vec4_instruction *last = (vec4_instruction *) instructions.get_tail(); in emit_thread_end()
237 vec4_instruction *inst = emit(MOV(mrf_reg, r0)); in emit_thread_end()
263 vec4_instruction *inst = emit(MOV(mrf_reg, r0)); in emit_urb_write_header()
270 vec4_instruction *
279 vec4_instruction *inst = emit(GS_OPCODE_URB_WRITE); in emit_urb_write_opcode()
360 vec4_instruction *inst = emit(MOV(mrf_reg, r0)); in emit_control_data_bits()
496 vec4_instruction *inst = in gs_emit_vertex()
|
| D | gen6_gs_visitor.cpp | 74 vec4_instruction *inst = emit(MOV(dst_reg(MRF, 1), in emit_prolog()
169 vec4_instruction *inst = emit(MOV(dst, src_reg(tmp))); in gs_emit_vertex()
225 vec4_instruction *inst = emit(CMP(dst_null_ud(), in gs_end_primitive()
293 vec4_instruction *inst = NULL; in emit_urb_write_opcode()
358 vec4_instruction *inst; in emit_thread_end()
417 vec4_instruction *inst = emit(MOV(reg, data)); in emit_thread_end()
479 vec4_instruction *inst = emit(GS_OPCODE_THREAD_END); in emit_thread_end()
612 vec4_instruction *inst = emit(MOV(dst_reg(destination_indices), in xfb_write()
666 vec4_instruction *inst = emit(GS_OPCODE_SVB_SET_DST_INDEX, in xfb_program()
|
| D | brw_vec4_tes.cpp | 61 foreach_block_and_inst(block, vec4_instruction, inst, cfg) { in setup_payload()
123 vec4_instruction *
132 vec4_instruction *inst = emit(VS_OPCODE_URB_WRITE); in emit_urb_write_opcode()
215 vec4_instruction *read = in nir_emit_intrinsic()
236 vec4_instruction *read = in nir_emit_intrinsic()
|
| D | brw_vec4_vs_visitor.cpp | 46 vec4_instruction *
55 vec4_instruction *inst = emit(VS_OPCODE_URB_WRITE); in emit_urb_write_opcode()
78 vec4_instruction *inst = emit_generic_urb_slot(reg, varying, 0); in emit_urb_slot()
|
| D | brw_vec4_copy_propagation.cpp | 44 is_direct_copy(vec4_instruction *inst) in is_direct_copy()
58 is_dominated_by_previous_instruction(vec4_instruction *inst) in is_dominated_by_previous_instruction()
67 is_channel_updated(vec4_instruction *inst, src_reg *values[4], int ch) in is_channel_updated()
136 vec4_instruction *inst, in try_constant_propagate()
319 vec4_instruction *inst, int arg, in try_copy_propagate()
484 foreach_block_and_inst(block, vec4_instruction, inst, cfg) { in opt_copy_propagation()
|
| D | brw_vec4_generator.cpp | 32 vec4_instruction *inst, in generate_math1_gen4()
55 vec4_instruction *inst, in generate_math_gen6()
74 vec4_instruction *inst, in generate_math2_gen4()
110 vec4_instruction *inst, in generate_tex()
346 generate_vs_urb_write(struct brw_codegen *p, vec4_instruction *inst) in generate_vs_urb_write()
360 generate_gs_urb_write(struct brw_codegen *p, vec4_instruction *inst) in generate_gs_urb_write()
375 generate_gs_urb_write_allocate(struct brw_codegen *p, vec4_instruction *inst) in generate_gs_urb_write_allocate()
400 generate_gs_thread_end(struct brw_codegen *p, vec4_instruction *inst) in generate_gs_thread_end()
492 vec4_instruction *inst, in generate_gs_svb_write()
534 vec4_instruction *inst, in generate_gs_svb_set_destination_index()
[all …]
|
| D | test_vec4_copy_propagation.cpp | 82 virtual vec4_instruction *emit_urb_write_opcode(bool complete) in emit_urb_write_opcode()
137 vec4_instruction *test_mov = in TEST_F()
166 vec4_instruction *test_mov = in TEST_F()
|
| D | brw_vec4_tcs.cpp | 100 vec4_instruction *inst; in emit_thread_end()
162 vec4_instruction *inst; in emit_input_urb_read()
197 vec4_instruction *inst; in emit_output_urb_read()
205 vec4_instruction *read = emit(VEC4_OPCODE_URB_READ, dst, src_reg(header)); in emit_output_urb_read()
228 vec4_instruction *inst; in emit_urb_write()
|
| D | brw_vec4_cmod_propagation.cpp | 44 foreach_inst_in_block_reverse_safe(vec4_instruction, inst, block) { in opt_cmod_propagation_local()
70 foreach_inst_in_block_reverse_starting_from(vec4_instruction, scan_inst, inst) { in opt_cmod_propagation_local()
|
| D | brw_vec4_tes.h | 57 virtual vec4_instruction *emit_urb_write_opcode(bool complete);
|
| D | brw_vec4_vs.h | 48 virtual vec4_instruction *emit_urb_write_opcode(bool complete);
|
| D | brw_vec4_nir.cpp | 106 vec4_instruction *inst = emit(MOV(dst_null_d(), condition)); in nir_emit_if()
457 vec4_instruction *inst = new(mem_ctx) in nir_emit_intrinsic()
458 vec4_instruction(SHADER_OPCODE_GET_BUFFER_SIZE, result_dst); in nir_emit_intrinsic()
1065 vec4_instruction *inst; in emit_find_msb_using_lzd()
1117 vec4_instruction *inst = emit(MOV(dst, brw_imm_f(src.df))); in emit_conversion_from_double()
1143 vec4_instruction *inst = emit(MOV(dst, src_reg(retype(temp2, dst.type)))); in emit_conversion_from_double()
1155 vec4_instruction *inst = emit(MOV(dst, src_reg(tmp_dst))); in emit_conversion_to_double()
1162 vec4_instruction *inst; in nir_emit_alu()
1589 vec4_instruction *inst = emit(MOV(dst_null_df(), value)); in nir_emit_alu()
2257 vec4_instruction *
[all …]
|
| D | brw_vec4_gs_visitor.h | 59 virtual vec4_instruction *emit_urb_write_opcode(bool complete);
|
| D | brw_vec4_tcs.h | 75 virtual vec4_instruction *emit_urb_write_opcode(bool complete) { return NULL; } in emit_urb_write_opcode()
|
| D | brw_vec4_live_variables.cpp | 73 foreach_inst_in_block(vec4_instruction, inst, block) { in setup_def_use()
255 foreach_block_and_inst(block, vec4_instruction, inst, cfg) { in calculate_live_intervals()
|
| D | test_vec4_cmod_propagation.cpp | 90 virtual vec4_instruction *emit_urb_write_opcode(bool complete) in emit_urb_write_opcode()
113 static vec4_instruction *
116 vec4_instruction *inst = (vec4_instruction *)block->start(); in instruction()
118 inst = (vec4_instruction *)inst->next; in instruction()
|
| D | brw_vec4_dead_code_eliminate.cpp | 56 foreach_inst_in_block_reverse_safe(vec4_instruction, inst, block) { in dead_code_eliminate()
|
| D | brw_schedule_instructions.cpp | 1250 vec4_instruction *inst = (vec4_instruction *)n->inst; in calculate_deps()
1338 vec4_instruction *inst = (vec4_instruction *)n->inst; in calculate_deps()
|