Home
last modified time | relevance | path

Searched refs:vminnm (Results 1 – 25 of 69) sorted by relevance

123

/external/llvm/test/CodeGen/ARM/
Dvminmaxnm-safe.ll25 ; CHECK: vminnm.f32 q{{[0-9]+}}, q{{[0-9]+}}, q{{[0-9]+}}
28 %tmp3 = call <4 x float> @llvm.arm.neon.vminnm.v4f32(<4 x float> %tmp1, <4 x float> %tmp2)
34 ; CHECK: vminnm.f32 d{{[0-9]+}}, d{{[0-9]+}}, d{{[0-9]+}}
37 %tmp3 = call <2 x float> @llvm.arm.neon.vminnm.v2f32(<2 x float> %tmp1, <2 x float> %tmp2)
45 ; CHECK-NOT: vminnm.f32
53 ; CHECK-NOT: vminnm.f64
61 ; CHECK-NOT: vminnm.f32
69 ; CHECK-NOT: vminnm.f64
77 ; CHECK-NOT: vminnm.f32
85 ; CHECK-NOT: vminnm.f32
[all …]
Dvminmaxnm.ll8 ; CHECK: vminnm.f32
17 ; CHECK: vminnm.f64
26 ; CHECK: vminnm.f32
35 ; CHECK: vminnm.f64
44 ; CHECK: vminnm.f32
53 ; CHECK: vminnm.f32
62 ; CHECK: vminnm.f32
71 ; CHECK: vminnm.f64
153 ; CHECK: vminnm.f32
154 ; CHECK: vminnm.f32
[all …]
/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/ARM/
Dvminmaxnm-safe.ll25 ; CHECK: vminnm.f32 q{{[0-9]+}}, q{{[0-9]+}}, q{{[0-9]+}}
28 %tmp3 = call <4 x float> @llvm.arm.neon.vminnm.v4f32(<4 x float> %tmp1, <4 x float> %tmp2)
34 ; CHECK: vminnm.f32 d{{[0-9]+}}, d{{[0-9]+}}, d{{[0-9]+}}
37 %tmp3 = call <2 x float> @llvm.arm.neon.vminnm.v2f32(<2 x float> %tmp1, <2 x float> %tmp2)
45 ; CHECK-NOT: vminnm.f32
53 ; CHECK-NOT: vminnm.f64
61 ; CHECK-NOT: vminnm.f32
69 ; CHECK-NOT: vminnm.f64
77 ; CHECK-NOT: vminnm.f32
85 ; CHECK-NOT: vminnm.f32
[all …]
Dvminmaxnm.ll8 ; CHECK: vminnm.f32
17 ; CHECK: vminnm.f64
26 ; CHECK: vminnm.f32
35 ; CHECK: vminnm.f64
44 ; CHECK: vminnm.f32
53 ; CHECK: vminnm.f32
62 ; CHECK: vminnm.f32
71 ; CHECK: vminnm.f64
153 ; CHECK: vminnm.f32
154 ; CHECK: vminnm.f32
[all …]
Dfp16-vminmaxnm.ll14 ; CHECK: vminnm.f16 s0, [[S2]], [[S0]]
27 ; CHECK: vminnm.f16 s0, [[S2]], [[S0]]
40 ; CHECK: vminnm.f16 s0, [[S2]], [[S0]]
53 ; CHECK: vminnm.f16 s0, [[S2]], [[S0]]
66 ; CHECK: vminnm.f16 s0, [[S2]], [[S0]]
172 ; CHECK: vminnm.f16 s0, [[S0]], [[S2]]
174 ; CHECK: vminnm.f16 s0, [[S0]], [[S2]]
188 ; CHECK: vminnm.f16 s0, [[S0]], [[S2]]
190 ; CHECK: vminnm.f16 s0, [[S0]], [[S2]]
204 ; CHECK: vminnm.f16 s0, [[S0]], [[S2]]
[all …]
Dfp16-vminmaxnm-safe.ll12 ; CHECK-NOT: vminnm.f16
23 ; CHECK-NOT: vminnm.f16
34 ; CHECK-NOT: vminnm.f16
45 ; CHECK-NOT: vminnm.f16
56 ; CHECK-NOT: vminnm.f16
149 ; CHECK: vminnm.f16 s2, [[S4]], [[S2]]
166 ; CHECK: vminnm.f16 s0, [[S0]], [[S2]]
181 ; CHECK: vminnm.f16 s2, [[S4]], [[S2]]
197 ; CHECK: vminnm.f16 s2, [[S4]], [[S2]]
216 ; CHECK: vminnm.f16 s0, [[S0]], [[S2]]
[all …]
/external/llvm/test/MC/ARM/
Dneon-v8.s7 vminnm.f32 d5, d4, d30
8 @ CHECK: vminnm.f32 d5, d4, d30 @ encoding: [0x3e,0x5f,0x24,0xf3]
9 vminnm.f32 q0, q13, q2
10 @ CHECK: vminnm.f32 q0, q13, q2 @ encoding: [0xd4,0x0f,0x2a,0xf3]
Dthumb-neon-v8.s7 vminnm.f32 d5, d4, d30
8 @ CHECK: vminnm.f32 d5, d4, d30 @ encoding: [0x24,0xff,0x3e,0x5f]
9 vminnm.f32 q0, q13, q2
10 @ CHECK: vminnm.f32 q0, q13, q2 @ encoding: [0x2a,0xff,0xd4,0x0f]
Dfp-armv8.s87 vminnm.f32 s0, s0, s12
88 @ CHECK: vminnm.f32 s0, s0, s12 @ encoding: [0x46,0x0a,0x80,0xfe]
89 vminnm.f64 d4, d6, d9
90 @ CHECK: vminnm.f64 d4, d6, d9 @ encoding: [0x49,0x4b,0x86,0xfe]
Dthumb-fp-armv8.s90 vminnm.f32 s0, s0, s12
91 @ CHECK: vminnm.f32 s0, s0, s12 @ encoding: [0x80,0xfe,0x46,0x0a]
92 vminnm.f64 d4, d6, d9
93 @ CHECK: vminnm.f64 d4, d6, d9 @ encoding: [0x86,0xfe,0x49,0x4b]
Ddirective-arch_extension-simd.s21 vminnm.f32 s0, s0, s0
26 vminnm.f64 d0, d0, d0
129 vminnm.f32 s0, s0, s0
134 vminnm.f64 d0, d0, d0
/external/swiftshader/third_party/llvm-7.0/llvm/test/MC/ARM/
Dthumb-neon-v8.s7 vminnm.f32 d5, d4, d30
8 @ CHECK: vminnm.f32 d5, d4, d30 @ encoding: [0x24,0xff,0x3e,0x5f]
9 vminnm.f32 q0, q13, q2
10 @ CHECK: vminnm.f32 q0, q13, q2 @ encoding: [0x2a,0xff,0xd4,0x0f]
Dneon-v8.s7 vminnm.f32 d5, d4, d30
8 @ CHECK: vminnm.f32 d5, d4, d30 @ encoding: [0x3e,0x5f,0x24,0xf3]
9 vminnm.f32 q0, q13, q2
10 @ CHECK: vminnm.f32 q0, q13, q2 @ encoding: [0xd4,0x0f,0x2a,0xf3]
Dthumb-fp-armv8.s90 vminnm.f32 s0, s0, s12
91 @ CHECK: vminnm.f32 s0, s0, s12 @ encoding: [0x80,0xfe,0x46,0x0a]
92 vminnm.f64 d4, d6, d9
93 @ CHECK: vminnm.f64 d4, d6, d9 @ encoding: [0x86,0xfe,0x49,0x4b]
Dfp-armv8.s87 vminnm.f32 s0, s0, s12
88 @ CHECK: vminnm.f32 s0, s0, s12 @ encoding: [0x46,0x0a,0x80,0xfe]
89 vminnm.f64 d4, d6, d9
90 @ CHECK: vminnm.f64 d4, d6, d9 @ encoding: [0x49,0x4b,0x86,0xfe]
Ddirective-arch_extension-simd.s21 vminnm.f32 s0, s0, s0
26 vminnm.f64 d0, d0, d0
129 vminnm.f32 s0, s0, s0
134 vminnm.f64 d0, d0, d0
Ddirective-arch_extension-fp.s32 vminnm.f32 s0, s0, s0
45 vminnm.f64 d0, d0, d0
168 vminnm.f32 s0, s0, s0
181 vminnm.f64 d0, d0, d0
/external/capstone/suite/MC/ARM/
Dthumb-neon-v8.s.cs4 0x24,0xff,0x3e,0x5f = vminnm.f32 d5, d4, d30
5 0x2a,0xff,0xd4,0x0f = vminnm.f32 q0, q13, q2
Dneon-v8.s.cs4 0x3e,0x5f,0x24,0xf3 = vminnm.f32 d5, d4, d30
5 0xd4,0x0f,0x2a,0xf3 = vminnm.f32 q0, q13, q2
Dthumb-fp-armv8.s.cs36 0x80,0xfe,0x46,0x0a = vminnm.f32 s0, s0, s12
37 0x86,0xfe,0x49,0x4b = vminnm.f64 d4, d6, d9
Dfp-armv8.s.cs36 0x46,0x0a,0x80,0xfe = vminnm.f32 s0, s0, s12
37 0x49,0x4b,0x86,0xfe = vminnm.f64 d4, d6, d9
/external/swiftshader/third_party/llvm-7.0/llvm/test/MC/Disassembler/ARM/
Dneon-v8.txt8 # CHECK: vminnm.f32 d5, d4, d30
10 # CHECK: vminnm.f32 q0, q13, q2
Dthumb-neon-v8.txt8 # CHECK: vminnm.f32 d5, d4, d30
10 # CHECK: vminnm.f32 q0, q13, q2
/external/llvm/test/MC/Disassembler/ARM/
Dneon-v8.txt8 # CHECK: vminnm.f32 d5, d4, d30
10 # CHECK: vminnm.f32 q0, q13, q2
Dthumb-neon-v8.txt8 # CHECK: vminnm.f32 d5, d4, d30
10 # CHECK: vminnm.f32 q0, q13, q2

123