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Searched refs:wdog (Results 1 – 25 of 30) sorted by relevance

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/external/u-boot/drivers/watchdog/
Dulp_wdog.c45 struct wdog_regs *wdog = (struct wdog_regs *)WDOG_BASE_ADDR; in hw_watchdog_set_timeout() local
47 writel(val, &wdog->toval); in hw_watchdog_set_timeout()
52 struct wdog_regs *wdog = (struct wdog_regs *)WDOG_BASE_ADDR; in hw_watchdog_reset() local
54 writel(REFRESH_WORD0, &wdog->cnt); in hw_watchdog_reset()
55 writel(REFRESH_WORD1, &wdog->cnt); in hw_watchdog_reset()
61 struct wdog_regs *wdog = (struct wdog_regs *)WDOG_BASE_ADDR; in hw_watchdog_init() local
63 writel(UNLOCK_WORD0, &wdog->cnt); in hw_watchdog_init()
64 writel(UNLOCK_WORD1, &wdog->cnt); in hw_watchdog_init()
66 val = readb(&wdog->cs2); in hw_watchdog_init()
68 writeb(val, &wdog->cs2); in hw_watchdog_init()
[all …]
Dimx_watchdog.c16 struct watchdog_regs *wdog = (struct watchdog_regs *)WDOG1_BASE_ADDR; in hw_watchdog_reset() local
18 writew(0x5555, &wdog->wsr); in hw_watchdog_reset()
19 writew(0xaaaa, &wdog->wsr); in hw_watchdog_reset()
24 struct watchdog_regs *wdog = (struct watchdog_regs *)WDOG1_BASE_ADDR; in hw_watchdog_init() local
37 WCR_WDA | SET_WCR_WT(timeout), &wdog->wcr); in hw_watchdog_init()
44 struct watchdog_regs *wdog = (struct watchdog_regs *)WDOG1_BASE_ADDR; in reset_cpu() local
46 clrsetbits_le16(&wdog->wcr, WCR_WT_MSK, WCR_WDE); in reset_cpu()
48 writew(0x5555, &wdog->wsr); in reset_cpu()
49 writew(0xaaaa, &wdog->wsr); /* load minimum 1/2 second timeout */ in reset_cpu()
/external/u-boot/arch/arm/mach-sunxi/
Dboard.c274 static const struct sunxi_wdog *wdog = in reset_cpu() local
275 &((struct sunxi_timer_reg *)SUNXI_TIMER_BASE)->wdog; in reset_cpu()
278 writel(WDT_MODE_RESET_EN | WDT_MODE_EN, &wdog->mode); in reset_cpu()
279 writel(WDT_CTRL_KEY | WDT_CTRL_RESTART, &wdog->ctl); in reset_cpu()
283 writel(WDT_MODE_RESET_EN | WDT_MODE_EN, &wdog->mode); in reset_cpu()
286 static const struct sunxi_wdog *wdog = in reset_cpu()
287 ((struct sunxi_timer_reg *)SUNXI_TIMER_BASE)->wdog; in reset_cpu()
290 writel(WDT_CFG_RESET, &wdog->cfg); in reset_cpu()
291 writel(WDT_MODE_EN, &wdog->mode); in reset_cpu()
292 writel(WDT_CTRL_KEY | WDT_CTRL_RESTART, &wdog->ctl); in reset_cpu()
/external/u-boot/drivers/mmc/
Ddavinci_mmc.c60 uint wdog = WATCHDOG_COUNT; in dmmc_wait_fifo_status() local
62 while (--wdog && ((get_val(&regs->mmcst1) & status) != status)) in dmmc_wait_fifo_status()
68 if (wdog == 0) in dmmc_wait_fifo_status()
77 uint wdog = WATCHDOG_COUNT; in dmmc_busy_wait() local
79 while (--wdog && (get_val(&regs->mmcst1) & MMCST1_BUSY)) in dmmc_busy_wait()
82 if (wdog == 0) in dmmc_busy_wait()
92 uint wdog = WATCHDOG_COUNT; in dmmc_check_status() local
95 while (wdog--) { in dmmc_check_status()
/external/u-boot/arch/arm/mach-imx/mx8m/
Dsoc.c60 void set_wdog_reset(struct wdog_regs *wdog) in set_wdog_reset() argument
69 setbits_le16(&wdog->wcr, WDOG_WDT_MASK | WDOG_WDZST_MASK); in set_wdog_reset()
216 struct watchdog_regs *wdog = (struct watchdog_regs *)WDOG1_BASE_ADDR; in reset_cpu() local
219 writew((WCR_WDE | WCR_SRS), &wdog->wcr); in reset_cpu()
/external/u-boot/arch/arm/mach-imx/mx7/
Dsoc.c239 void set_wdog_reset(struct wdog_regs *wdog) in set_wdog_reset() argument
241 u32 reg = readw(&wdog->wcr); in set_wdog_reset()
247 reg = readw(&wdog->wcr); in set_wdog_reset()
254 writew(reg, &wdog->wcr); in set_wdog_reset()
Dpsci-mx7.c88 struct wdog_regs *wdog = (struct wdog_regs *)WDOG1_BASE_ADDR; in imx_system_reset() local
93 writew(WCR_WDE, &wdog->wcr); in imx_system_reset()
/external/u-boot/arch/arm/mach-davinci/
Ddm365_lowlevel.c266 struct davinci_timer *wdog = in dm365_por_reset() local
275 writel(DV_WDT_ENABLE_SYS_RESET, &wdog->na1); in dm365_por_reset()
276 writel(DV_WDT_TRIGGER_SYS_RESET, &wdog->na2); in dm365_por_reset()
284 struct davinci_timer *wdog = in dm365_wdt_reset() local
296 writel(DV_WDT_ENABLE_SYS_RESET, &wdog->na1); in dm365_wdt_reset()
297 writel(DV_WDT_TRIGGER_SYS_RESET, &wdog->na2); in dm365_wdt_reset()
/external/u-boot/board/warp7/
Dwarp7.c205 struct wdog_regs *wdog = (struct wdog_regs *)WDOG1_BASE_ADDR; in board_late_init() local
213 set_wdog_reset(wdog); in board_late_init()
219 clrsetbits_le16(&wdog->wcr, 0, 0x10); in board_late_init()
/external/u-boot/arch/arm/include/asm/arch-sunxi/
Dtimer.h70 struct sunxi_wdog wdog; /* 0x90 */ member
81 struct sunxi_wdog wdog[5]; /* We have 5 watchdogs */ member
/external/u-boot/board/compulab/cl-som-imx7/
Dcl-som-imx7.c301 struct wdog_regs *wdog = (struct wdog_regs *)WDOG1_BASE_ADDR; in cl_som_imx7_setup_wdog() local
304 set_wdog_reset(wdog); in cl_som_imx7_setup_wdog()
309 clrsetbits_le16(&wdog->wcr, 0, 0x10); in cl_som_imx7_setup_wdog()
/external/u-boot/board/technexion/pico-imx7d/
Dpico-imx7d.c263 struct wdog_regs *wdog = (struct wdog_regs *)WDOG1_BASE_ADDR; in board_late_init() local
267 set_wdog_reset(wdog); in board_late_init()
273 clrsetbits_le16(&wdog->wcr, 0, 0x10); in board_late_init()
/external/u-boot/board/freescale/mx7dsabresd/
Dmx7dsabresd.c368 struct wdog_regs *wdog = (struct wdog_regs *)WDOG1_BASE_ADDR; in board_late_init() local
372 set_wdog_reset(wdog); in board_late_init()
378 clrsetbits_le16(&wdog->wcr, 0, 0x10); in board_late_init()
/external/u-boot/arch/m68k/cpu/mcf523x/
Dcpu_init.c40 wdog_t *wdog = (wdog_t *) MMAP_WDOG; in cpu_init_f() local
45 out_be16(&wdog->cr, 0); in cpu_init_f()
/external/u-boot/arch/arm/include/asm/arch-mx7/
Dsys_proto.h10 void set_wdog_reset(struct wdog_regs *wdog);
/external/u-boot/arch/arm/include/asm/arch-mx8m/
Dsys_proto.h11 void set_wdog_reset(struct wdog_regs *wdog);
/external/u-boot/arch/arm/mach-bcm283x/include/mach/
Dwdog.h19 u32 wdog; member
/external/u-boot/arch/arm/cpu/armv7/ls102xa/
Dcpu.c372 struct watchdog_regs *wdog = (struct watchdog_regs *)WDOG1_BASE_ADDR; in reset_cpu() local
374 clrbits_be16(&wdog->wcr, WCR_SRS); in reset_cpu()
/external/u-boot/arch/arm/mach-bcm283x/
Dreset.c49 writel(BCM2835_WDOG_PASSWORD | timeout, &wdog_regs->wdog); in reset_cpu()
/external/u-boot/arch/m68k/cpu/mcf532x/
Dcpu_init.c211 wdog_t *wdog = (wdog_t *) MMAP_WDOG; in cpu_init_f() local
214 out_be16(&wdog->cr, 0); in cpu_init_f()
/external/u-boot/arch/arm/dts/
Dfsl-imx8mq.dtsi384 wdog1: wdog@30280000 {
392 wdog2: wdog@30290000 {
400 wdog3: wdog@302a0000 {
Dimx7s.dtsi432 wdog1: wdog@30280000 {
439 wdog2: wdog@30290000 {
447 wdog3: wdog@302a0000 {
455 wdog4: wdog@302b0000 {
Dimx7ulp.dtsi347 wdog1: wdog@403D0000 {
362 wdog2: wdog@40430000 {
Dimx6ul.dtsi494 wdog1: wdog@020bc000 {
501 wdog2: wdog@020c0000 {
879 wdog3: wdog@021e4000 {
Dimx6ull.dtsi587 wdog1: wdog@020bc000 {
594 wdog2: wdog@020c0000 {
1029 wdog3: wdog@021e4000 {

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