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Searched refs:write_aux_reg (Results 1 – 4 of 4) sorted by relevance

/external/u-boot/arch/arc/lib/
Dcache.c287 write_aux_reg(ARC_AUX_SLC_CTRL, ctrl); in __slc_entire_op()
290 write_aux_reg(ARC_AUX_SLC_INVALIDATE, 0x1); in __slc_entire_op()
292 write_aux_reg(ARC_AUX_SLC_FLUSH, 0x1); in __slc_entire_op()
315 write_aux_reg(ARC_AUX_SLC_RGN_END1, 0); in slc_upper_region_init()
316 write_aux_reg(ARC_AUX_SLC_RGN_START1, 0); in slc_upper_region_init()
348 write_aux_reg(ARC_AUX_SLC_CTRL, ctrl); in __slc_rgn_op()
362 write_aux_reg(ARC_AUX_SLC_RGN_END, end); in __slc_rgn_op()
363 write_aux_reg(ARC_AUX_SLC_RGN_START, paddr); in __slc_rgn_op()
401 write_aux_reg(ARC_AUX_IO_COH_AP0_SIZE, in arc_ioc_setup()
404 write_aux_reg(ARC_AUX_IO_COH_AP0_BASE, ap_base >> 12); in arc_ioc_setup()
[all …]
/external/u-boot/drivers/timer/
Darc_timer.c75 write_aux_reg(ARC_AUX_TIMER0_CTRL, NH_MODE); in arc_timer_probe()
77 write_aux_reg(ARC_AUX_TIMER0_LIMIT, 0xffffffff); in arc_timer_probe()
79 write_aux_reg(ARC_AUX_TIMER0_CNT, 0); in arc_timer_probe()
83 write_aux_reg(ARC_AUX_TIMER1_CTRL, NH_MODE); in arc_timer_probe()
85 write_aux_reg(ARC_AUX_TIMER1_LIMIT, 0xffffffff); in arc_timer_probe()
87 write_aux_reg(ARC_AUX_TIMER1_CNT, 0); in arc_timer_probe()
/external/u-boot/arch/arc/include/asm/
Darcregs.h86 #define write_aux_reg(reg_immed, val) \ macro
/external/u-boot/board/synopsys/hsdk/
Dhsdk.c196 write_aux_reg(ARC_AUX_ICCM_BASE, val << APERTURE_SHIFT); in init_slave_cpu_func()
201 write_aux_reg(ARC_AUX_DCCM_BASE, val << APERTURE_SHIFT); in init_slave_cpu_func()
219 write_aux_reg(ARC_AUX_NON_VOLATILE_LIMIT, val); in init_cluster_nvlim()
220 write_aux_reg(AUX_AUX_CACHE_LIMIT, val); in init_cluster_nvlim()