| /external/spirv-llvm/lib/SPIRV/ |
| D | OCLUtil.cpp | 164 unsigned ExtOp = ~0U; in getSPIRVInst() local
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| D | SPIRVWriter.cpp | 344 SPIRVWord *ExtOp, in isBuiltinTransToExtInst()
1196 SPIRVWord ExtOp = SPIRVWORD_MAX; in transCallInst() local
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| D | OCL20ToSPIRV.cpp | 958 unsigned ExtOp = ~0U; in transBuiltin() local
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| D | SPIRVUtil.cpp | 410 getSPIRVExtFuncName(SPIRVExtInstSetKind Set, unsigned ExtOp, in getSPIRVExtFuncName()
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/CodeGen/SelectionDAG/ |
| D | LegalizeDAG.cpp | 4392 unsigned ExtOp, TruncOp; in PromoteNode() local
4425 unsigned ExtOp = Node->getOpcode() == ISD::UMUL_LOHI ? ISD::ZERO_EXTEND in PromoteNode() local
4441 unsigned ExtOp, TruncOp; in PromoteNode() local
4481 unsigned ExtOp = ISD::FP_EXTEND; in PromoteNode() local
4494 unsigned ExtOp = ISD::FP_EXTEND; in PromoteNode() local
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| D | DAGCombiner.cpp | 11657 unsigned ExtOp = IsInputSigned && IsOutputSigned ? ISD::SIGN_EXTEND in FoldIntToFPToInt() local
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| /external/llvm/lib/CodeGen/SelectionDAG/ |
| D | LegalizeDAG.cpp | 4095 unsigned ExtOp, TruncOp; in PromoteNode() local
4113 unsigned ExtOp, TruncOp; in PromoteNode() local
4153 unsigned ExtOp = ISD::FP_EXTEND; in PromoteNode() local
4166 unsigned ExtOp = ISD::FP_EXTEND; in PromoteNode() local
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| D | DAGCombiner.cpp | 9104 unsigned ExtOp = IsInputSigned && IsOutputSigned ? ISD::SIGN_EXTEND in FoldIntToFPToInt() local
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| /external/spirv-llvm/lib/SPIRV/libSPIRV/ |
| D | SPIRVEntry.cpp | 102 unsigned ExtOp) { in create_unique()
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AMDGPU/ |
| D | AMDGPUCodeGenPrepare.cpp | 384 Value *ExtOp = Builder.CreateZExt(I.getOperand(0), I32Ty); in promoteUniformBitreverseToI32() local
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| D | SIISelLowering.cpp | 6990 unsigned ExtOp = Signed ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND; in performIntMed3ImmCombine() local
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| /external/swiftshader/third_party/LLVM/lib/CodeGen/SelectionDAG/ |
| D | LegalizeDAG.cpp | 3883 unsigned ExtOp, TruncOp; in PromoteNode() local
3901 unsigned ExtOp, TruncOp; in PromoteNode() local
3941 unsigned ExtOp = ISD::FP_EXTEND; in PromoteNode() local
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| /external/llvm/lib/Target/NVPTX/ |
| D | NVPTXISelLowering.cpp | 2186 ISD::LoadExtType ExtOp = Ins[InsIdx].Flags.isSExt() ? in LowerFormalArguments() local
2312 ISD::LoadExtType ExtOp = Ins[InsIdx].Flags.isSExt() ? in LowerFormalArguments() local
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| /external/llvm/lib/Transforms/Scalar/ |
| D | IndVarSimplify.cpp | 1244 Value *ExtOp = createExtendInst(Op, WideType, Cmp->isSigned(), Cmp); in widenLoopCompare() local
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Hexagon/ |
| D | HexagonConstExtenders.cpp | 1530 MachineOperand ExtOp(EV); in insertInitializer() local
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Transforms/Scalar/ |
| D | IndVarSimplify.cpp | 1365 Value *ExtOp = createExtendInst(Op, WideType, Cmp->isSigned(), Cmp); in widenLoopCompare() local
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/PowerPC/ |
| D | PPCISelLowering.cpp | 5763 unsigned ExtOp = Flags.isSExt() ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND; in LowerCall_64SVR4() local
6326 unsigned ExtOp = Flags.isSExt() ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND; in LowerCall_Darwin() local
12011 ConstantSDNode *ExtOp = dyn_cast<ConstantSDNode>(Extract.getOperand(1)); in combineBVOfVecSExt() local
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| /external/llvm/lib/Target/PowerPC/ |
| D | PPCISelLowering.cpp | 5201 unsigned ExtOp = Flags.isSExt() ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND; in LowerCall_64SVR4() local
5769 unsigned ExtOp = Flags.isSExt() ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND; in LowerCall_Darwin() local
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| /external/swiftshader/third_party/LLVM/lib/Target/PowerPC/ |
| D | PPCISelLowering.cpp | 3162 unsigned ExtOp = Flags.isSExt() ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND; in LowerCall_Darwin() local
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| /external/clang/lib/CodeGen/ |
| D | CGBuiltin.cpp | 3782 Value *ExtOp, Value *IndexOp, in packTBLDVectorList()
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| /external/llvm/lib/Target/ARM/ |
| D | ARMISelLowering.cpp | 8806 unsigned ExtOp = VT.bitsGT(tmp.getValueType()) ? ISD::ANY_EXTEND : ISD::TRUNCATE; in AddCombineToVPADDL() local
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/X86/ |
| D | X86ISelLowering.cpp | 15492 SDValue ExtOp = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, ExtVecVT, in InsertBitToMaskVector() local
32285 SDValue ExtOp = DAG.getNode(OpCode, dl, MVT::i32, SrcOp, in combineExtractWithShuffle() local
39571 unsigned ExtOp = InOpcode == X86ISD::VZEXT ? ISD::ZERO_EXTEND_VECTOR_INREG in combineExtractSubvector() local
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| /external/swiftshader/third_party/LLVM/lib/Target/X86/ |
| D | X86ISelLowering.cpp | 5680 SDValue ExtOp = (EltIdx < 8) in LowerVECTOR_SHUFFLEv8i16() local
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/ARM/ |
| D | ARMISelLowering.cpp | 9974 unsigned ExtOp = VT.bitsGT(tmp.getValueType()) ? ISD::ANY_EXTEND : ISD::TRUNCATE; in AddCombineBUILD_VECTORToVPADDL() local
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| /external/llvm/lib/Target/X86/ |
| D | X86ISelLowering.cpp | 12539 SDValue ExtOp = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, ExtVecVT, in InsertBitToMaskVector() local
14617 SDValue ExtOp = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i8, Op); in EmitTest() local
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