| /external/swiftshader/third_party/llvm-7.0/llvm/lib/CodeGen/ |
| D | RegisterScavenging.cpp | 560 unsigned SReg = findSurvivorReg(I, Candidates, 25, UseMI); in scavengeRegister() local
660 unsigned SReg = RS.scavengeRegisterBackwards(RC, DefMI.getIterator(), in scavengeVReg() local
700 unsigned SReg = scavengeVReg(MRI, RS, Reg, true); in scavengeFrameVirtualRegsInBlock() local
726 unsigned SReg = scavengeVReg(MRI, RS, Reg, false); in scavengeFrameVirtualRegsInBlock() local
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| D | LivePhysRegs.cpp | 268 for (MCSuperRegIterator SReg(Reg, &TRI); SReg.isValid(); ++SReg) { in addLiveIns() local
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| /external/swiftshader/third_party/llvm-7.0/llvm/include/llvm/CodeGen/ |
| D | VirtRegMap.h | 134 void setIsSplitFromReg(unsigned virtReg, unsigned SReg) { in setIsSplitFromReg()
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| /external/llvm/include/llvm/CodeGen/ |
| D | VirtRegMap.h | 138 void setIsSplitFromReg(unsigned virtReg, unsigned SReg) { in setIsSplitFromReg()
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/ARM/ |
| D | A15SDOptimizer.cpp | 145 unsigned A15SDOptimizer::getDPRLaneFromSPR(unsigned SReg) { in getDPRLaneFromSPR()
154 unsigned A15SDOptimizer::getPrefSPRLane(unsigned SReg) { in getPrefSPRLane()
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| D | ARMBaseInstrInfo.cpp | 4613 unsigned SReg, unsigned &Lane) { in getCorrespondingDRegAndLane()
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| /external/llvm/lib/Target/AMDGPU/ |
| D | SIShrinkInstructions.cpp | 352 unsigned SReg = Src2->getReg(); in runOnMachineFunction() local
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| /external/llvm/lib/Target/ARM/ |
| D | A15SDOptimizer.cpp | 147 unsigned A15SDOptimizer::getDPRLaneFromSPR(unsigned SReg) { in getDPRLaneFromSPR()
156 unsigned A15SDOptimizer::getPrefSPRLane(unsigned SReg) { in getPrefSPRLane()
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| D | ARMBaseInstrInfo.cpp | 4218 unsigned SReg, unsigned &Lane) { in getCorrespondingDRegAndLane()
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| /external/swiftshader/third_party/LLVM/lib/CodeGen/ |
| D | RegisterScavenging.cpp | 356 unsigned SReg = findSurvivorReg(I, Candidates, 25, UseMI); in scavengeRegister() local
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| D | VirtRegMap.h | 217 void setIsSplitFromReg(unsigned virtReg, unsigned SReg) { in setIsSplitFromReg()
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| D | VirtRegRewriter.cpp | 533 unsigned SReg = *SR; in ResurrectKill() local
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AMDGPU/ |
| D | SIShrinkInstructions.cpp | 454 unsigned SReg = Src2->getReg(); in runOnMachineFunction() local
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| D | SIInstrInfo.cpp | 690 unsigned SReg = MRI.createVirtualRegister(&AMDGPU::SReg_64_XEXECRegClass); in insertVectorSelect() local
701 unsigned SReg = MRI.createVirtualRegister(&AMDGPU::SReg_64_XEXECRegClass); in insertVectorSelect() local
712 unsigned SReg = MRI.createVirtualRegister(&AMDGPU::SReg_64_XEXECRegClass); in insertVectorSelect() local
725 unsigned SReg = MRI.createVirtualRegister(&AMDGPU::SReg_64_XEXECRegClass); in insertVectorSelect() local
737 unsigned SReg = MRI.createVirtualRegister(&AMDGPU::SReg_64_XEXECRegClass); in insertVectorSelect() local
747 unsigned SReg = MRI.createVirtualRegister(&AMDGPU::SReg_64_XEXECRegClass); in insertVectorSelect() local
761 unsigned SReg = MRI.createVirtualRegister(&AMDGPU::SReg_64_XEXECRegClass); in insertVectorSelect() local
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| /external/llvm/lib/CodeGen/ |
| D | RegisterScavenging.cpp | 373 unsigned SReg = findSurvivorReg(I, Candidates, 25, UseMI); in scavengeRegister() local
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| D | BranchFolding.cpp | 414 for (MCSuperRegIterator SReg(Reg, TRI); SReg.isValid(); ++SReg) { in computeLiveIns() local
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| /external/swiftshader/third_party/LLVM/lib/Target/PowerPC/ |
| D | PPCRegisterInfo.cpp | 596 unsigned SReg; in eliminateFrameIndex() local
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/PowerPC/ |
| D | PPCRegisterInfo.cpp | 979 SReg = MF.getRegInfo().createVirtualRegister(RC); in eliminateFrameIndex() local
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| /external/llvm/lib/Target/PowerPC/ |
| D | PPCRegisterInfo.cpp | 888 SReg = MF.getRegInfo().createVirtualRegister(RC); in eliminateFrameIndex() local
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| /external/llvm/lib/Target/Mips/AsmParser/ |
| D | MipsAsmParser.cpp | 3387 unsigned SReg = Inst.getOperand(1).getReg(); in expandRotation() local
3452 unsigned SReg = Inst.getOperand(1).getReg(); in expandRotationImm() local
3516 unsigned SReg = Inst.getOperand(1).getReg(); in expandDRotation() local
3581 unsigned SReg = Inst.getOperand(1).getReg(); in expandDRotationImm() local
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| /external/swiftshader/third_party/LLVM/lib/Target/ARM/ |
| D | ARMAsmPrinter.cpp | 244 unsigned SReg = Reg - ARM::S0; in EmitDwarfRegOp() local
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Mips/AsmParser/ |
| D | MipsAsmParser.cpp | 4415 unsigned SReg = Inst.getOperand(1).getReg(); in expandRotation() local
4478 unsigned SReg = Inst.getOperand(1).getReg(); in expandRotationImm() local
4540 unsigned SReg = Inst.getOperand(1).getReg(); in expandDRotation() local
4603 unsigned SReg = Inst.getOperand(1).getReg(); in expandDRotationImm() local
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| /external/clang/include/clang/StaticAnalyzer/Core/PathSensitive/ |
| D | MemRegion.h | 1080 const MemRegion *SReg) in CXXBaseObjectRegion()
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| /external/clang/lib/StaticAnalyzer/Core/ |
| D | MemRegion.cpp | 409 const MemRegion *SReg) { in ProfileRegion()
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| /external/swiftshader/third_party/subzero/src/ |
| D | IceAssemblerARM32.cpp | 205 IValueT SReg = EncodedQReg << 2; in mapQRegToSReg() local
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