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/external/pcre/dist2/testdata/
Dtestoutput22-82 # for DFA matching in UTF mode, so this test is not run with -dfa. The output
3 # of this test is different in 8-, 16-, and 32-bit modes. Some tests may match
16 # This should produce an error diagnostic (\C in UTF lookbehind) in 8-bit and
17 # 16-bit modes, but not in 32-bit mode.
19 /(?<=ab\Cde)X/utf
20 Failed: error 136 at offset 0: \C is not allowed in a lookbehind assertion in UTF-8 mode
25 /\C+\X \X+\C/Bx
26 ------------------------------------------------------------------
34 ------------------------------------------------------------------
36 /\C+\X \X+\C/Bx,utf
[all …]
Dtestinput51 # This set of tests checks the API, internals, and non-Perl stuff for UTF
3 # results in 8-bit, 16-bit, and 32-bit modes are excluded (see tests 10 and
11 # However, it *is* in that file for Unicode 10, but when I came to re-check,
14 # 2066-2069 are graphic and printable according to Perl, though they are
19 \x{061c}
23 \x{61c}
24 \x{2066}
25 \x{2067}
26 \x{2068}
27 \x{2069}
[all …]
Dtestoutput51 # This set of tests checks the API, internals, and non-Perl stuff for UTF
3 # results in 8-bit, 16-bit, and 32-bit modes are excluded (see tests 10 and
11 # However, it *is* in that file for Unicode 10, but when I came to re-check,
14 # 2066-2069 are graphic and printable according to Perl, though they are
19 \x{061c}
20 0: \x{61c}
24 \x{61c}
26 \x{2066}
28 \x{2067}
30 \x{2068}
[all …]
Dtestoutput22-162 # for DFA matching in UTF mode, so this test is not run with -dfa. The output
3 # of this test is different in 8-, 16-, and 32-bit modes. Some tests may match
16 # This should produce an error diagnostic (\C in UTF lookbehind) in 8-bit and
17 # 16-bit modes, but not in 32-bit mode.
19 /(?<=ab\Cde)X/utf
20 Failed: error 136 at offset 0: \C is not allowed in a lookbehind assertion in UTF-16 mode
25 /\C+\X \X+\C/Bx
26 ------------------------------------------------------------------
34 ------------------------------------------------------------------
36 /\C+\X \X+\C/Bx,utf
[all …]
/external/llvm/test/CodeGen/ARM/
Dvbits.ll1 ; RUN: llc -mtriple=arm-eabi -mattr=+neon -mcpu=cortex-a8 %s -o - | FileCheck %s
3 define <8 x i8> @v_andi8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
4 ;CHECK-LABEL: v_andi8:
6 %tmp1 = load <8 x i8>, <8 x i8>* %A
7 %tmp2 = load <8 x i8>, <8 x i8>* %B
8 %tmp3 = and <8 x i8> %tmp1, %tmp2
9 ret <8 x i8> %tmp3
12 define <4 x i16> @v_andi16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
13 ;CHECK-LABEL: v_andi16:
15 %tmp1 = load <4 x i16>, <4 x i16>* %A
[all …]
Dvshl.ll1 ; RUN: llc -mtriple=arm-eabi -mattr=+neon %s -o - | FileCheck %s
3 define <8 x i8> @vshls8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
4 ;CHECK-LABEL: vshls8:
6 %tmp1 = load <8 x i8>, <8 x i8>* %A
7 %tmp2 = load <8 x i8>, <8 x i8>* %B
8 %tmp3 = call <8 x i8> @llvm.arm.neon.vshifts.v8i8(<8 x i8> %tmp1, <8 x i8> %tmp2)
9 ret <8 x i8> %tmp3
12 define <4 x i16> @vshls16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
13 ;CHECK-LABEL: vshls16:
15 %tmp1 = load <4 x i16>, <4 x i16>* %A
[all …]
/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/AArch64/
Dminmax-of-minmax.ll2 ; RUN: llc < %s -mtriple=aarch64-unknown-unknown | FileCheck %s
10 define <4 x i32> @smin_ab_bc(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) {
11 ; CHECK-LABEL: smin_ab_bc:
13 ; CHECK-NEXT: smin v0.4s, v0.4s, v1.4s
14 ; CHECK-NEXT: smin v1.4s, v1.4s, v2.4s
15 ; CHECK-NEXT: smin v0.4s, v0.4s, v1.4s
16 ; CHECK-NEXT: ret
17 %cmp_ab = icmp slt <4 x i32> %a, %b
18 %min_ab = select <4 x i1> %cmp_ab, <4 x i32> %a, <4 x i32> %b
19 %cmp_bc = icmp slt <4 x i32> %b, %c
[all …]
/external/llvm/test/CodeGen/Hexagon/
Dv60Intrins.ll1 ; RUN: llc -march=hexagon -mcpu=hexagonv60 -O2 -disable-post-ra < %s | FileCheck %s
3 ; CHECK: q{{[0-3]}} = vand(v{{[0-9]*}},r{{[0-9]*}})
4 ; CHECK: q{{[0-3]}} = vsetq(r{{[0-9]*}})
5 ; CHECK: q{{[0-3]}} |= vand(v{{[0-9]*}},r{{[0-9]*}})
6 ; CHECK: v{{[0-9]*}} = vand(q{{[0-3]}},r{{[0-9]*}})
7 ; CHECK: q{{[0-3]}} = vcmp.eq(v{{[0-9]*}}.b,v{{[0-9]*}}.b)
8 ; CHECK: v{{[0-9]*}} = vand(q{{[0-3]}},r{{[0-9]*}})
9 ; CHECK: q{{[0-3]}} = vcmp.eq(v{{[0-9]*}}.h,v{{[0-9]*}}.h)
10 ; CHECK: v{{[0-9]*}} = vand(q{{[0-3]}},r{{[0-9]*}})
11 ; CHECK: q{{[0-3]}} = vcmp.eq(v{{[0-9]*}}.w,v{{[0-9]*}}.w)
[all …]
/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/Hexagon/
Dv60Intrins.ll1 ; RUN: llc -march=hexagon -mcpu=hexagonv60 -O2 -disable-post-ra < %s | FileCheck %s
3 ; CHECK: q{{[0-3]}} = vand(v{{[0-9]*}},r{{[0-9]*}})
4 ; CHECK: q{{[0-3]}} |= vand(v{{[0-9]*}},r{{[0-9]*}})
5 ; CHECK: v{{[0-9]*}} = vand(q{{[0-3]}},r{{[0-9]*}})
6 ; CHECK: q{{[0-3]}} = vcmp.eq(v{{[0-9]*}}.b,v{{[0-9]*}}.b)
7 ; CHECK: v{{[0-9]*}} = vand(q{{[0-3]}},r{{[0-9]*}})
8 ; CHECK: q{{[0-3]}} = vcmp.eq(v{{[0-9]*}}.h,v{{[0-9]*}}.h)
9 ; CHECK: v{{[0-9]*}} = vand(q{{[0-3]}},r{{[0-9]*}})
10 ; CHECK: q{{[0-3]}} = vcmp.eq(v{{[0-9]*}}.w,v{{[0-9]*}}.w)
11 ; CHECK: v{{[0-9]*}} = vand(q{{[0-3]}},r{{[0-9]*}})
[all …]
Dintrinsics-v60-alu.ll1 ; RUN: llc -march=hexagon < %s | FileCheck %s
3 ; CHECK-LABEL: test1:
4 ; CHECK: v{{[0-9]+}} = vand(v{{[0-9]+}},v{{[0-9]+}})
5 define <16 x i32> @test1(<16 x i32> %a, <16 x i32> %b) #0 {
7 %0 = tail call <16 x i32> @llvm.hexagon.V6.vand(<16 x i32> %a, <16 x i32> %b)
8 ret <16 x i32> %0
11 ; CHECK-LABEL: test2:
12 ; CHECK: v{{[0-9]+}} = vor(v{{[0-9]+}},v{{[0-9]+}})
13 define <16 x i32> @test2(<16 x i32> %a, <16 x i32> %b) #0 {
15 %0 = tail call <16 x i32> @llvm.hexagon.V6.vor(<16 x i32> %a, <16 x i32> %b)
[all …]
/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/ARM/
Dvshl.ll1 ; RUN: llc -mtriple=arm-eabi -mattr=+neon %s -o - | FileCheck %s
3 define <8 x i8> @vshls8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
4 ;CHECK-LABEL: vshls8:
6 %tmp1 = load <8 x i8>, <8 x i8>* %A
7 %tmp2 = load <8 x i8>, <8 x i8>* %B
8 %tmp3 = call <8 x i8> @llvm.arm.neon.vshifts.v8i8(<8 x i8> %tmp1, <8 x i8> %tmp2)
9 ret <8 x i8> %tmp3
12 define <4 x i16> @vshls16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
13 ;CHECK-LABEL: vshls16:
15 %tmp1 = load <4 x i16>, <4 x i16>* %A
[all …]
/external/clang/test/OpenMP/
Datomic_messages.cpp1 // RUN: %clang_cc1 -verify -fopenmp -ferror-limit 100 %s
7 …-error@+2 {{the statement for 'atomic' must be an expression statement of form '++x;', '--x;', 'x+… in foo()
8 // expected-note@+1 {{expected an expression statement}} in foo()
11 goto L1; // expected-error {{use of undeclared label 'L1'}} in foo()
13 goto L2; // expected-error {{use of undeclared label 'L2'}} in foo()
15 …-error@+2 {{the statement for 'atomic' must be an expression statement of form '++x;', '--x;', 'x+… in foo()
16 // expected-note@+1 {{expected an expression statement}} in foo()
43 …// expected-error@+2 {{the statement for 'atomic read' must be an expression statement of form 'v … in read()
44 // expected-note@+1 {{expected an expression statement}} in read()
47 …// expected-error@+2 {{the statement for 'atomic read' must be an expression statement of form 'v … in read()
[all …]
Datomic_messages.c1 // RUN: %clang_cc1 -verify -fopenmp -ferror-limit 100 %s
7 …-error@+2 {{the statement for 'atomic' must be an expression statement of form '++x;', '--x;', 'x+… in foo()
8 // expected-note@+1 {{expected an expression statement}} in foo()
11 goto L1; // expected-error {{use of undeclared label 'L1'}} in foo()
13 goto L2; // expected-error {{use of undeclared label 'L2'}} in foo()
15 …-error@+2 {{the statement for 'atomic' must be an expression statement of form '++x;', '--x;', 'x+… in foo()
16 // expected-note@+1 {{expected an expression statement}} in foo()
34 …// expected-error@+2 {{the statement for 'atomic read' must be an expression statement of form 'v … in readint()
35 // expected-note@+1 {{expected an expression statement}} in readint()
38 …// expected-error@+2 {{the statement for 'atomic read' must be an expression statement of form 'v … in readint()
[all …]
/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/PowerPC/
Dvec_cmp.ll1 ; RUN: llc -verify-machineinstrs -mcpu=pwr6 -mattr=+altivec < %s | FileCheck %s
3 ; Check vector comparisons using altivec. For non-native types, just basic
9 target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v…
10 target triple = "powerpc64-unknown-linux-gnu"
12 define <2 x i8> @v2si8_cmp(<2 x i8> %x, <2 x i8> %y) nounwind readnone {
13 %cmp = icmp eq <2 x i8> %x, %y
14 %sext = sext <2 x i1> %cmp to <2 x i8>
15 ret <2 x i8> %sext
17 ; CHECK-LABEL: v2si8_cmp:
18 ; CHECK: vcmpequb {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}
[all …]
/external/llvm/test/CodeGen/PowerPC/
Dvec_cmp.ll1 ; RUN: llc -mcpu=pwr6 -mattr=+altivec < %s | FileCheck %s
3 ; Check vector comparisons using altivec. For non-native types, just basic
9 target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v…
10 target triple = "powerpc64-unknown-linux-gnu"
12 define <2 x i8> @v2si8_cmp(<2 x i8> %x, <2 x i8> %y) nounwind readnone {
13 %cmp = icmp eq <2 x i8> %x, %y
14 %sext = sext <2 x i1> %cmp to <2 x i8>
15 ret <2 x i8> %sext
17 ; CHECK-LABEL: v2si8_cmp:
18 ; CHECK: vcmpequb {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}
[all …]
/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/X86/
Davx512-cvttp2i.ll2 ; RUN: llc < %s -mtriple=x86_64-- -mattr=avx512f,avx512vl,avx512dq | FileCheck %s --check-prefixes=…
4 ; PR37751 - https://bugs.llvm.org/show_bug.cgi?id=37751
5 ; We can't combine into 'round' instructions because the behavior is different for out-of-range val…
7 declare <16 x i32> @llvm.x86.avx512.mask.cvttps2dq.512(<16 x float>, <16 x i32>, i16, i32)
8 declare <4 x i32> @llvm.x86.avx512.mask.cvttps2udq.128(<4 x float>, <4 x i32>, i8)
9 declare <8 x i32> @llvm.x86.avx512.mask.cvttps2udq.256(<8 x float>, <8 x i32>, i8)
10 declare <16 x i32> @llvm.x86.avx512.mask.cvttps2udq.512(<16 x float>, <16 x i32>, i16, i32)
11 declare <4 x i32> @llvm.x86.avx512.mask.cvttpd2udq.256(<4 x double>, <4 x i32>, i8)
12 declare <8 x i32> @llvm.x86.avx512.mask.cvttpd2dq.512(<8 x double>, <8 x i32>, i8, i32)
13 declare <8 x i32> @llvm.x86.avx512.mask.cvttpd2udq.512(<8 x double>, <8 x i32>, i8, i32)
[all …]
Dxop-intrinsics-x86_64.ll2 ; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx,+fma4,+xop | FileCheck %s
4 define <2 x double> @test_int_x86_xop_vpermil2pd(<2 x double> %a0, <2 x double> %a1, <2 x i64> %a2)…
5 ; CHECK-LABEL: test_int_x86_xop_vpermil2pd:
7 ; CHECK-NEXT: vpermil2pd $1, %xmm2, %xmm1, %xmm0, %xmm0
8 ; CHECK-NEXT: retq
9 …%res = call <2 x double> @llvm.x86.xop.vpermil2pd(<2 x double> %a0, <2 x double> %a1, <2 x i64> %a…
10 ret <2 x double> %res
12 define <2 x double> @test_int_x86_xop_vpermil2pd_mr(<2 x double> %a0, <2 x double>* %a1, <2 x i64> …
13 ; CHECK-LABEL: test_int_x86_xop_vpermil2pd_mr:
15 ; CHECK-NEXT: vpermil2pd $1, %xmm1, (%rdi), %xmm0, %xmm0
[all …]
Davx512-rndscale.ll2 ; RUN: llc < %s -disable-peephole -mtriple=x86_64-apple-darwin -mattr=+avx512vl | FileCheck %s
4 declare <2 x double> @llvm.floor.v2f64(<2 x double> %p)
5 declare <4 x float> @llvm.floor.v4f32(<4 x float> %p)
6 declare <4 x double> @llvm.floor.v4f64(<4 x double> %p)
7 declare <8 x float> @llvm.floor.v8f32(<8 x float> %p)
8 declare <8 x double> @llvm.floor.v8f64(<8 x double> %p)
9 declare <16 x float> @llvm.floor.v16f32(<16 x float> %p)
10 declare <2 x double> @llvm.ceil.v2f64(<2 x double> %p)
11 declare <4 x float> @llvm.ceil.v4f32(<4 x float> %p)
12 declare <4 x double> @llvm.ceil.v4f64(<4 x double> %p)
[all …]
/external/mesa3d/src/intel/isl/
Disl_format.c52 #define x 255 macro
68 * smpl - Sampling Engine
69 * filt - Sampling Engine Filtering
70 * shad - Sampling Engine Shadow Map
71 * CK - Sampling Engine Chroma Key
72 * RT - Render Target
73 * AB - Alpha Blend Render Target
74 * VB - Input Vertex Buffer
75 * SO - Steamed Output Vertex Buffers (transform feedback)
76 * color - Color Processing
[all …]
/external/fonttools/Tests/varLib/data/test_results/
DBuild.ttx1 <?xml version="1.0" encoding="UTF-8"?>
9 <!-- RegionAxisCount=2 -->
10 <!-- RegionCount=5 -->
13 <StartCoord value="-1.0"/>
14 <PeakCoord value="-1.0"/>
49 <StartCoord value="-1.0"/>
50 <PeakCoord value="-1.0"/>
72 <!-- VarDataCount=1 -->
74 <!-- ItemCount=6 -->
76 <!-- VarRegionCount=2 -->
[all …]
/external/llvm/test/CodeGen/X86/
Dxop-intrinsics-x86_64-upgrade.ll2 ; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx,+fma4,+xop | FileCheck %s
4 define <2 x double> @test_int_x86_xop_vpermil2pd(<2 x double> %a0, <2 x double> %a1, <2 x double> %…
5 ; CHECK-LABEL: test_int_x86_xop_vpermil2pd:
7 ; CHECK-NEXT: vpermil2pd $1, %xmm2, %xmm1, %xmm0, %xmm0
8 ; CHECK-NEXT: retq
9 …%res = call <2 x double> @llvm.x86.xop.vpermil2pd(<2 x double> %a0, <2 x double> %a1, <2 x double>…
10 ret <2 x double> %res
12 define <2 x double> @test_int_x86_xop_vpermil2pd_mr(<2 x double> %a0, <2 x double>* %a1, <2 x doubl…
13 ; CHECK-LABEL: test_int_x86_xop_vpermil2pd_mr:
15 ; CHECK-NEXT: vpermil2pd $1, %xmm1, (%rdi), %xmm0, %xmm0
[all …]
Davx512vl-vec-cmp.ll2 ; RUN: llc < %s -mtriple=x86_64-apple-darwin -mcpu=skx | FileCheck %s
4 define <4 x i64> @test256_1(<4 x i64> %x, <4 x i64> %y) nounwind {
5 ; CHECK-LABEL: test256_1:
7 ; CHECK-NEXT: vpcmpeqq %ymm1, %ymm0, %k1
8 ; CHECK-NEXT: vpblendmq %ymm0, %ymm1, %ymm0 {%k1}
9 ; CHECK-NEXT: retq
10 %mask = icmp eq <4 x i64> %x, %y
11 %max = select <4 x i1> %mask, <4 x i64> %x, <4 x i64> %y
12 ret <4 x i64> %max
15 define <4 x i64> @test256_2(<4 x i64> %x, <4 x i64> %y, <4 x i64> %x1) nounwind {
[all …]
Dxop-intrinsics-fast-isel.ll2 ; RUN: llc < %s -fast-isel -mtriple=i686-unknown-unknown -mattr=+avx,+fma4,+xop | FileCheck %s --ch…
3 ; RUN: llc < %s -fast-isel -mtriple=x86_64-unknown-unknown -mattr=+avx,+fma4,+xop | FileCheck %s --…
5 ; NOTE: This should use IR equivalent to what is generated by clang/test/CodeGen/xop-builtins.c
7 define <2 x i64> @test_mm_maccs_epi16(<2 x i64> %a0, <2 x i64> %a1, <2 x i64> %a2) nounwind {
8 ; X32-LABEL: test_mm_maccs_epi16:
10 ; X32-NEXT: vpmacssww %xmm2, %xmm1, %xmm0, %xmm0
11 ; X32-NEXT: retl
13 ; X64-LABEL: test_mm_maccs_epi16:
15 ; X64-NEXT: vpmacssww %xmm2, %xmm1, %xmm0, %xmm0
16 ; X64-NEXT: retq
[all …]
Dxop-intrinsics-x86_64.ll2 ; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx,+fma4,+xop | FileCheck %s
4 define <2 x double> @test_int_x86_xop_vpermil2pd(<2 x double> %a0, <2 x double> %a1, <2 x i64> %a2)…
5 ; CHECK-LABEL: test_int_x86_xop_vpermil2pd:
7 ; CHECK-NEXT: vpermil2pd $1, %xmm2, %xmm1, %xmm0, %xmm0
8 ; CHECK-NEXT: retq
9 …%res = call <2 x double> @llvm.x86.xop.vpermil2pd(<2 x double> %a0, <2 x double> %a1, <2 x i64> %a…
10 ret <2 x double> %res
12 define <2 x double> @test_int_x86_xop_vpermil2pd_mr(<2 x double> %a0, <2 x double>* %a1, <2 x i64> …
13 ; CHECK-LABEL: test_int_x86_xop_vpermil2pd_mr:
15 ; CHECK-NEXT: vpermil2pd $1, %xmm1, (%rdi), %xmm0, %xmm0
[all …]
/external/swiftshader/third_party/LLVM/test/CodeGen/ARM/
Dvshl.ll1 ; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s
3 define <8 x i8> @vshls8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
6 %tmp1 = load <8 x i8>* %A
7 %tmp2 = load <8 x i8>* %B
8 %tmp3 = call <8 x i8> @llvm.arm.neon.vshifts.v8i8(<8 x i8> %tmp1, <8 x i8> %tmp2)
9 ret <8 x i8> %tmp3
12 define <4 x i16> @vshls16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
15 %tmp1 = load <4 x i16>* %A
16 %tmp2 = load <4 x i16>* %B
17 %tmp3 = call <4 x i16> @llvm.arm.neon.vshifts.v4i16(<4 x i16> %tmp1, <4 x i16> %tmp2)
[all …]

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