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Searched refs:src_reg (Results 1 – 6 of 6) sorted by relevance

/art/runtime/interpreter/
Dinterpreter_common.cc1490 size_t dest_reg, size_t src_reg) in AssignRegister() argument
1493 uint32_t src_value = shadow_frame.GetVReg(src_reg); in AssignRegister()
1494 ObjPtr<mirror::Object> o = shadow_frame.GetVRegReference<kVerifyNone>(src_reg); in AssignRegister()
1515 for (size_t src_reg = first_src_reg, dest_reg = first_dest_reg; dest_reg < dest_reg_bound; in CopyRegisters() local
1516 ++dest_reg, ++src_reg) { in CopyRegisters()
1517 AssignRegister(callee_frame, caller_frame, dest_reg, src_reg); in CopyRegisters()
1660 const size_t src_reg = (is_range) ? vregC + arg_offset : arg[arg_offset]; in DoCallCommon() local
1664 ObjPtr<mirror::Object> o = shadow_frame.GetVRegReference(src_reg); in DoCallCommon()
1696 (static_cast<uint64_t>(shadow_frame.GetVReg(src_reg + 1)) << BitSizeOf<uint32_t>()) | in DoCallCommon()
1697 static_cast<uint32_t>(shadow_frame.GetVReg(src_reg)); in DoCallCommon()
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/art/compiler/dex/
Dinline_method_analyser.cc666 uint32_t src_reg = instruction->VRegA_22c(); in AnalyseIPutMethod() local
671 DCHECK_GE(src_reg, arg_start); in AnalyseIPutMethod()
672 DCHECK_LT(opcode == Instruction::IPUT_WIDE ? src_reg + 1 : src_reg, code_item->RegistersSize()); in AnalyseIPutMethod()
674 uint32_t src_arg = src_reg - arg_start; in AnalyseIPutMethod()
/art/runtime/
Dmethod_handles.cc319 size_t src_reg = operands->GetOperand(i); in CopyArgumentsFromCallerFrame() local
321 uint32_t src_value = caller_frame.GetVReg(src_reg); in CopyArgumentsFromCallerFrame()
322 ObjPtr<mirror::Object> o = caller_frame.GetVRegReference<kVerifyNone>(src_reg); in CopyArgumentsFromCallerFrame()
/art/compiler/optimizing/
Dcode_generator_mips.cc6217 Register src_reg = ZERO; in GenConditionalMoveR2() local
6251 src_reg = src.AsRegister<Register>(); in GenConditionalMoveR2()
6253 src_reg = src.AsRegisterPairLow<Register>(); in GenConditionalMoveR2()
6264 __ Movz(dst.AsRegister<Register>(), src_reg, cond_reg); in GenConditionalMoveR2()
6266 __ Movn(dst.AsRegister<Register>(), src_reg, cond_reg); in GenConditionalMoveR2()
6271 __ Movz(dst.AsRegisterPairLow<Register>(), src_reg, cond_reg); in GenConditionalMoveR2()
6274 __ Movn(dst.AsRegisterPairLow<Register>(), src_reg, cond_reg); in GenConditionalMoveR2()
6302 __ Movf(dst.AsRegister<Register>(), src_reg, cond_cc); in GenConditionalMoveR2()
6304 __ Movt(dst.AsRegister<Register>(), src_reg, cond_cc); in GenConditionalMoveR2()
6309 __ Movf(dst.AsRegisterPairLow<Register>(), src_reg, cond_cc); in GenConditionalMoveR2()
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Dcode_generator_mips64.cc4745 FpuRegister src_reg = false_src.AsFpuRegister<FpuRegister>(); in GenConditionalMove() local
4747 __ SelnezS(dst_reg, src_reg, fcond_reg); in GenConditionalMove()
4749 __ SeleqzS(dst_reg, src_reg, fcond_reg); in GenConditionalMove()
4752 FpuRegister src_reg = true_src.AsFpuRegister<FpuRegister>(); in GenConditionalMove() local
4754 __ SeleqzS(dst_reg, src_reg, fcond_reg); in GenConditionalMove()
4756 __ SelnezS(dst_reg, src_reg, fcond_reg); in GenConditionalMove()
4780 FpuRegister src_reg = false_src.AsFpuRegister<FpuRegister>(); in GenConditionalMove() local
4782 __ SelnezD(dst_reg, src_reg, fcond_reg); in GenConditionalMove()
4784 __ SeleqzD(dst_reg, src_reg, fcond_reg); in GenConditionalMove()
4787 FpuRegister src_reg = true_src.AsFpuRegister<FpuRegister>(); in GenConditionalMove() local
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Dcode_generator_x86.cc1290 XmmRegister src_reg = source.AsFpuRegister<XmmRegister>(); in Move64() local
1291 __ movd(destination.AsRegisterPairLow<Register>(), src_reg); in Move64()
1292 __ psrlq(src_reg, Immediate(32)); in Move64()
1293 __ movd(destination.AsRegisterPairHigh<Register>(), src_reg); in Move64()
6244 XmmRegister src_reg = source.AsFpuRegister<XmmRegister>(); in EmitMove() local
6245 __ movd(destination.AsRegisterPairLow<Register>(), src_reg); in EmitMove()
6246 __ psrlq(src_reg, Immediate(32)); in EmitMove()
6247 __ movd(destination.AsRegisterPairHigh<Register>(), src_reg); in EmitMove()