| /device/linaro/bootloader/edk2/ArmVirtPkg/Library/FdtPciHostBridgeLib/ |
| D | FdtPciHostBridgeLib.c | 88 OUT UINT64 *IoBase, in ProcessPciHost() argument
114 *IoBase = 0; in ProcessPciHost()
209 *IoBase = SwapBytes64 (Record->ChildBase); in ProcessPciHost()
211 IoTranslation = SwapBytes64 (Record->CpuBase) - *IoBase; in ProcessPciHost()
267 __FUNCTION__, ConfigBase, ConfigSize, *BusMin, *BusMax, *IoBase, *IoSize, in ProcessPciHost()
289 UINT64 IoBase, IoSize; in PciHostBridgeGetRootBridges() local
302 Status = ProcessPciHost (&IoBase, &IoSize, &Mmio32Base, &Mmio32Size, in PciHostBridgeGetRootBridges()
328 mRootBridge.Io.Base = IoBase; in PciHostBridgeGetRootBridges()
329 mRootBridge.Io.Limit = IoBase + IoSize - 1; in PciHostBridgeGetRootBridges()
|
| /device/linaro/bootloader/edk2/CorebootModulePkg/Library/BaseSerialPortLib16550/ |
| D | BaseSerialPortLib16550.c | 197 UINT32 IoBase; in GetSerialRegisterBase() local
274 IoBase = PciRead8 (PciLibAddress + OFFSET_OF (PCI_TYPE01, Bridge.IoBase)); in GetSerialRegisterBase()
275 if ((IoBase & PCI_BRIDGE_32_BIT_IO_SPACE ) == 0) { in GetSerialRegisterBase()
276 IoBase = IoBase >> 4; in GetSerialRegisterBase()
278 …IoBase = (PciRead16 (PciLibAddress + OFFSET_OF (PCI_TYPE01, Bridge.IoBaseUpper16)) << 4) | (IoBase… in GetSerialRegisterBase()
284 if (IoLimit < IoBase) { in GetSerialRegisterBase()
291 if (IoBase < ParentIoBase || IoBase > ParentIoLimit || IoLimit > ParentIoLimit) { in GetSerialRegisterBase()
294 ParentIoBase = IoBase; in GetSerialRegisterBase()
|
| /device/linaro/bootloader/edk2/MdeModulePkg/Library/BaseSerialPortLib16550/ |
| D | BaseSerialPortLib16550.c | 197 UINT32 IoBase; in GetSerialRegisterBase() local
274 IoBase = PciRead8 (PciLibAddress + OFFSET_OF (PCI_TYPE01, Bridge.IoBase)); in GetSerialRegisterBase()
275 if ((IoBase & PCI_BRIDGE_32_BIT_IO_SPACE ) == 0) { in GetSerialRegisterBase()
276 IoBase = IoBase >> 4; in GetSerialRegisterBase()
278 …IoBase = (PciRead16 (PciLibAddress + OFFSET_OF (PCI_TYPE01, Bridge.IoBaseUpper16)) << 4) | (IoBase… in GetSerialRegisterBase()
284 if (IoLimit < IoBase) { in GetSerialRegisterBase()
291 if (IoBase < ParentIoBase || IoBase > ParentIoLimit || IoLimit > ParentIoLimit) { in GetSerialRegisterBase()
294 ParentIoBase = IoBase; in GetSerialRegisterBase()
|
| /device/linaro/bootloader/edk2/ArmVirtPkg/Library/FdtPciPcdProducerLib/ |
| D | FdtPciPcdProducerLib.c | 58 UINT64 IoBase; in GetPciIoTranslation() local
78 IoBase = SwapBytes64 (Record->ChildBase); in GetPciIoTranslation()
79 *IoTranslation = SwapBytes64 (Record->CpuBase) - IoBase; in GetPciIoTranslation()
|
| /device/linaro/bootloader/edk2/DuetPkg/PciRootBridgeNoEnumerationDxe/ |
| D | PcatPciRootBridge.c | 105 PrivateData->IoBase = 0xffffffff; in InitializePcatPciRootBridge()
251 Value = PciConfigurationHeader.Bridge.IoBase & 0x0f; in InitializePcatPciRootBridge()
252 Base = ((UINT32)PciConfigurationHeader.Bridge.IoBase & 0xf0) << 8; in InitializePcatPciRootBridge()
259 if (PrivateData->IoBase > Base) { in InitializePcatPciRootBridge()
260 PrivateData->IoBase = Base; in InitializePcatPciRootBridge()
434 PrivateData->IoBase = 0; in InitializePcatPciRootBridge()
572 if (PrivateData->IoLimit >= PrivateData->IoBase) { in ConstructConfiguration()
651 if (PrivateData->IoLimit >= PrivateData->IoBase) { in ConstructConfiguration()
656 Configuration->AddrRangeMin = PrivateData->IoBase; in ConstructConfiguration()
866 if (PrivateData->IoBase > Base) { in PcatPciRootBridgeParseBars()
[all …]
|
| D | PcatPciRootBridge.h | 66 UINT64 IoBase; // Offsets host to bus io addr. member
|
| /device/linaro/bootloader/edk2/Vlv2TbltDevicePkg/PlatformInitPei/ |
| D | MemoryCallback.c | 150 UINT32 IoBase; in MemoryDiscoveredPpiNotifyCallback()
216 …IoBase = MmPci32( 0, DEFAULT_PCI_BUS_NUMBER_PCH, PCI_DEVICE_NUMBER_PCH_LPC, 0, R_PCH_LPC_IO_BASE )… in MemoryDiscoveredPpiNotifyCallback()
220 IoBase, in MemoryDiscoveredPpiNotifyCallback()
223 DEBUG ((EFI_D_INFO, "IoBase : 0x%x\n", IoBase)); in MemoryDiscoveredPpiNotifyCallback()
|
| D | PchInitPeim.c | 619 UINT32 IoBase;
655 PchPlatformPolicyPpi->IoBase = IO_BASE_ADDRESS;
712 IoBase = MmioRead32 (MmPciAddress (0,
718 MmioAnd32 ((UINTN) (IoBase + 0x270), (UINT32) (~0x07));
|
| /device/linaro/bootloader/edk2/QuarkPlatformPkg/Pci/Dxe/PciHostBridge/ |
| D | PciHostResource.h | 36 UINTN IoBase; member
|
| D | PciHostBridge.c | 164 PrivateData->Aperture.IoBase = PcdGet16 (PcdPciHostBridgeIoBase); in InitializePciHostBridge()
411 … if (RootBridgeInstance->Aperture.IoBase < RootBridgeInstance->Aperture.IoLimit) { in NotifyPhase()
418 BaseAddress = RootBridgeInstance->Aperture.IoBase; in NotifyPhase()
|
| /device/linaro/bootloader/edk2/MdeModulePkg/Bus/Pci/PciBusDxe/ |
| D | PciEnumerator.c | 1339 OUT UINT64 *IoBase, in GetResourceBase() argument
1352 *IoBase = 0xFFFFFFFFFFFFFFFFULL; in GetResourceBase()
1399 *IoBase = Ptr->AddrRangeMin; in GetResourceBase()
1497 UINT64 IoBase; in PciBridgeResourceAllocator() local
1563 &IoBase, in PciBridgeResourceAllocator()
1578 IoBase, in PciBridgeResourceAllocator()
1646 OUT UINT64 *IoBase, in GetResourceBaseFromBridge() argument
1657 *IoBase = gAllOne; in GetResourceBaseFromBridge()
1666 *IoBase = Bridge->PciBar[PPB_IO_RANGE].BaseAddress; in GetResourceBaseFromBridge()
1687 *IoBase = Bridge->PciBar[P2C_IO_1].BaseAddress; in GetResourceBaseFromBridge()
[all …]
|
| D | PciEnumerator.h | 280 OUT UINT64 *IoBase,
333 OUT UINT64 *IoBase,
|
| D | PciLib.c | 370 UINT64 IoBase; in PciHostBridgeResourceAllocator() local
787 &IoBase, in PciHostBridgeResourceAllocator()
819 IoBase, in PciHostBridgeResourceAllocator()
855 IoBridge ->PciDev->PciBar[IoBridge ->Bar].BaseAddress = IoBase; in PciHostBridgeResourceAllocator()
|
| /device/linaro/bootloader/edk2/DuetPkg/PciBusNoEnumerationDxe/ |
| D | PciDeviceSupport.c | 494 if ((((PciData.Bridge.IoBase & 0xF) == 0) && in EnableBridgeAttributes()
495 (PciData.Bridge.IoBase != 0 || PciData.Bridge.IoLimit != 0)) || in EnableBridgeAttributes()
496 (((PciData.Bridge.IoBase & 0xF) == 1) && in EnableBridgeAttributes()
497 …((PciData.Bridge.IoBase & 0xF0) != 0 || (PciData.Bridge.IoLimit & 0xF0) != 0 || PciData.Bridge.IoB… in EnableBridgeAttributes()
|
| /device/linaro/bootloader/edk2/Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Include/Ppi/ |
| D | PchPlatformPolicy.h | 151 UINT32 IoBase; // IO Base Address. member
|
| /device/linaro/bootloader/OpenPlatformPkg/Chips/Hisilicon/Drivers/PciHostBridgeDxe/ |
| D | PciRootBridgeIo.c | 687 void SetAtuIoRW(UINT64 RbPciBase,UINT64 IoBase,UINT64 CpuIoRegionLimit, UINT64 CpuIoRegionBase, UIN… in SetAtuIoRW() argument
696 MmioWrite32 (RbPciBase + IATU_OFFSET + IATU_REGION_TARGET_LOW, (UINT32)(IoBase)); in SetAtuIoRW()
697 … MmioWrite32 (RbPciBase + IATU_OFFSET + IATU_REGION_TARGET_HIGH, (UINT32)((UINT64)(IoBase) >> 32)); in SetAtuIoRW()
736 SetAtuIoRW (Private->RbPciBar, Private->IoBase, Private->IoLimit, Private->CpuIoRegionBase, 3); in InitAtu()
796 PrivateData->IoBase = ResAppeture->IoBase; in RootBridgeConstructor()
971 Base = PrivateData->IoBase; in RootBridgeIoCheckParameter()
1166 Address -= PrivateData->IoBase; in RootBridgeIoIoRW()
|
| D | PciHostBridge.h | 468 UINT64 IoBase; member
|
| /device/linaro/bootloader/OpenPlatformPkg/Drivers/Net/Lan91xDxe/ |
| D | Lan91xDxe.c | 72 UINTN IoBase; // I/O Base Address member
223 MmioWrite16 (LanDriver->IoBase + LAN91X_BANK_OFFSET, Bank); in SelectIoBank()
243 return MmioRead16 (LanDriver->IoBase + Offset); in ReadIoReg16()
262 return MmioWrite16 (LanDriver->IoBase + Offset, Value); in WriteIoReg16()
280 return MmioRead8 (LanDriver->IoBase + Offset); in ReadIoReg8()
299 return MmioWrite8 (LanDriver->IoBase + Offset, Value); in WriteIoReg8()
451 Value = MmioRead16 (LanDriver->IoBase + LAN91X_BANK_OFFSET); in PrintIoRegisters()
900 Bank = MmioRead16 (LanDriver->IoBase + LAN91X_BANK_OFFSET); in Probe()
910 Bank = MmioRead16 (LanDriver->IoBase + LAN91X_BANK_OFFSET); in Probe()
2133 LanDriver->IoBase = PcdGet32 (PcdLan91xDxeBaseAddress); in Lan91xDxeEntry()
|
| /device/linaro/bootloader/edk2/Vlv2TbltDevicePkg/PlatformPei/ |
| D | Platform.c | 224 UINT32 IoBase = 0; in DetermineTurbotBoard()
233 IoBase = MmioRead32 (PciD31F0RegBase + R_PCH_LPC_IO_BASE) & B_PCH_LPC_IO_BASE_BAR; in DetermineTurbotBoard()
235 MmioConf0 = IoBase + SSUSOffset + PConf0Offset; in DetermineTurbotBoard()
236 MmioPadval = IoBase + SSUSOffset + PValueOffset; in DetermineTurbotBoard()
|
| /device/linaro/bootloader/edk2/OvmfPkg/Library/PciHostBridgeLib/ |
| D | XenSupport.c | 279 Value = Pci.Bridge.IoBase & 0x0f; in ScanForRootBridges()
280 Base = ((UINT32) Pci.Bridge.IoBase & 0xf0) << 8; in ScanForRootBridges()
|
| /device/linaro/bootloader/edk2/DuetPkg/PciRootBridgeNoEnumerationDxe/Ipf/ |
| D | PcatIo.c | 80 if ( Address < PrivateData->IoBase || Address > PrivateData->IoLimit ) { in PcatRootBridgeIoIoRead()
183 if ( Address < PrivateData->IoBase || Address > PrivateData->IoLimit ) { in PcatRootBridgeIoIoWrite()
|
| /device/linaro/bootloader/edk2/CorebootPayloadPkg/Library/PciHostBridgeLib/ |
| D | PciHostBridgeSupport.c | 405 Value = Pci.Bridge.IoBase & 0x0f; in ScanForRootBridges()
406 Base = ((UINT32) Pci.Bridge.IoBase & 0xf0) << 8; in ScanForRootBridges()
|
| /device/linaro/bootloader/OpenPlatformPkg/Chips/Hisilicon/Include/Library/ |
| D | PlatformPciLib.h | 198 UINT64 IoBase; member
|
| /device/linaro/bootloader/edk2/ShellPkg/Library/UefiShellDebug1CommandsLib/ |
| D | Pci.h | 371 UINT8 IoBase; // I/O Base member
|
| /device/linaro/bootloader/edk2/EdkCompatibilityPkg/Foundation/Include/IndustryStandard/ |
| D | pci22.h | 78 UINT8 IoBase; member
|