Searched refs:tzdram_base (Results 1 – 6 of 6) sorted by relevance
157 plat_bl31_params_from_bl2.tzdram_base = plat_params->tzdram_base; in bl31_early_platform_setup()165 if ((plat_bl31_params_from_bl2.tzdram_base != BL31_BASE) && in bl31_early_platform_setup()191 tegra_memctrl_tzdram_setup(plat_bl31_params_from_bl2.tzdram_base, in bl31_early_platform_setup()204 tzdram_start = plat_bl31_params_from_bl2.tzdram_base; in bl31_early_platform_setup()205 tzdram_end = plat_bl31_params_from_bl2.tzdram_base + in bl31_early_platform_setup()318 mmap_add_region(params_from_bl2->tzdram_base, in bl31_plat_arch_setup()319 params_from_bl2->tzdram_base, in bl31_plat_arch_setup()
250 tegra_memctrl_tzdram_setup(plat_params->tzdram_base, in tegra_pwr_domain_on_finish()
69 uint64_t tzdram_base = params_from_bl2->tzdram_base; in tegra_smmu_save_context() local70 uint64_t tzdram_end = tzdram_base + params_from_bl2->tzdram_size; in tegra_smmu_save_context()80 assert((smmu_ctx_addr >= tzdram_base) && (smmu_ctx_addr <= tzdram_end)); in tegra_smmu_save_context()
46 cpu_reset_handler_base = params_from_bl2->tzdram_base; in plat_secondary_setup()
126 smmu_ctx_base = params_from_bl2->tzdram_base + in tegra_soc_pwr_domain_suspend()247 val = params_from_bl2->tzdram_base + in tegra_soc_pwr_domain_power_down_wfi()
28 uint64_t tzdram_base; member