1 /* 2 * Copyright (c) 2015, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <arch_helpers.h> 8 #include <debug.h> 9 #include <mce.h> 10 #include <mmio.h> 11 #include <string.h> 12 #include <tegra_def.h> 13 #include <tegra_private.h> 14 15 #define MISCREG_CPU_RESET_VECTOR 0x2000 16 #define MISCREG_AA64_RST_LOW 0x2004 17 #define MISCREG_AA64_RST_HIGH 0x2008 18 19 #define SCRATCH_SECURE_RSV1_SCRATCH_0 0x658 20 #define SCRATCH_SECURE_RSV1_SCRATCH_1 0x65C 21 22 #define CPU_RESET_MODE_AA64 1 23 24 extern uint64_t tegra_bl31_phys_base; 25 extern uint64_t __tegra186_cpu_reset_handler_end; 26 27 /******************************************************************************* 28 * Setup secondary CPU vectors 29 ******************************************************************************/ plat_secondary_setup(void)30void plat_secondary_setup(void) 31 { 32 uint32_t addr_low, addr_high; 33 plat_params_from_bl2_t *params_from_bl2 = bl31_get_plat_params(); 34 uint64_t cpu_reset_handler_base; 35 36 INFO("Setting up secondary CPU boot\n"); 37 38 if ((tegra_bl31_phys_base >= TEGRA_TZRAM_BASE) && 39 (tegra_bl31_phys_base <= (TEGRA_TZRAM_BASE + TEGRA_TZRAM_SIZE))) { 40 41 /* 42 * The BL31 code resides in the TZSRAM which loses state 43 * when we enter System Suspend. Copy the wakeup trampoline 44 * code to TZDRAM to help us exit from System Suspend. 45 */ 46 cpu_reset_handler_base = params_from_bl2->tzdram_base; 47 memcpy16((void *)((uintptr_t)cpu_reset_handler_base), 48 (void *)(uintptr_t)tegra186_cpu_reset_handler, 49 (uintptr_t)&__tegra186_cpu_reset_handler_end - 50 (uintptr_t)tegra186_cpu_reset_handler); 51 52 } else { 53 cpu_reset_handler_base = (uintptr_t)tegra_secure_entrypoint; 54 } 55 56 addr_low = (uint32_t)cpu_reset_handler_base | CPU_RESET_MODE_AA64; 57 addr_high = (uint32_t)((cpu_reset_handler_base >> 32) & 0x7ff); 58 59 /* write lower 32 bits first, then the upper 11 bits */ 60 mmio_write_32(TEGRA_MISC_BASE + MISCREG_AA64_RST_LOW, addr_low); 61 mmio_write_32(TEGRA_MISC_BASE + MISCREG_AA64_RST_HIGH, addr_high); 62 63 /* save reset vector to be used during SYSTEM_SUSPEND exit */ 64 mmio_write_32(TEGRA_SCRATCH_BASE + SCRATCH_SECURE_RSV1_SCRATCH_0, 65 addr_low); 66 mmio_write_32(TEGRA_SCRATCH_BASE + SCRATCH_SECURE_RSV1_SCRATCH_1, 67 addr_high); 68 69 /* update reset vector address to the CCPLEX */ 70 mce_update_reset_vector(); 71 } 72