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/device/linaro/bootloader/arm-trusted-firmware/plat/rockchip/common/include/
Dplat_macros.S51 mrs x7, id_aa64pfr0_el1
52 ubfx x7, x7, #ID_AA64PFR0_GIC_SHIFT, #ID_AA64PFR0_GIC_WIDTH
53 cmp x7, #1
83 add x7, x16, #GICD_ISPENDR
87 sub x4, x7, x16
95 ldr x4, [x7], #8
106 mov_imm x7, (PLAT_RK_CCI_BASE + SLAVE_IFACE_OFFSET( \
108 ldr w8, [x7, #SNOOP_CTRL_REG]
110 mov_imm x7, (PLAT_RK_CCI_BASE + SLAVE_IFACE_OFFSET( \
112 ldr w9, [x7, #SNOOP_CTRL_REG]
/device/linaro/bootloader/arm-trusted-firmware/plat/mediatek/mt8173/include/
Dplat_macros.S47 add x7, x16, #GICD_ISPENDR
51 sub x4, x7, x16
59 ldr x4, [x7], #8
69 mov_imm x7, (PLAT_MT_CCI_BASE + SLAVE_IFACE_OFFSET( \
71 ldr w8, [x7, #SNOOP_CTRL_REG]
73 mov_imm x7, (PLAT_MT_CCI_BASE + SLAVE_IFACE_OFFSET( \
75 ldr w9, [x7, #SNOOP_CTRL_REG]
/device/linaro/bootloader/arm-trusted-firmware/plat/hisilicon/hikey960/include/
Dplat_macros.S50 add x7, x16, #GICD_ISPENDR
54 sub x4, x7, x16
60 ldr x4, [x7], #8
68 mov_imm x7, (CCI400_REG_BASE + SLAVE_IFACE_OFFSET( \
70 ldr w8, [x7, #SNOOP_CTRL_REG]
72 mov_imm x7, (CCI400_REG_BASE + SLAVE_IFACE_OFFSET( \
74 ldr w9, [x7, #SNOOP_CTRL_REG]
/device/linaro/bootloader/arm-trusted-firmware/plat/mediatek/mt6795/include/
Dplat_macros.S42 add x7, x16, #GICD_ISPENDR
46 sub x4, x7, x16
54 ldr x4, [x7], #8
77 mov_imm x7, (PLAT_MT_CCI_BASE + SLAVE_IFACE_OFFSET( \
79 ldr w8, [x7, #SNOOP_CTRL_REG]
81 mov_imm x7, (PLAT_MT_CCI_BASE + SLAVE_IFACE_OFFSET( \
83 ldr w9, [x7, #SNOOP_CTRL_REG]
/device/linaro/bootloader/arm-trusted-firmware/plat/hisilicon/hikey/include/
Dplat_macros.S50 add x7, x16, #GICD_ISPENDR
54 sub x4, x7, x16
60 ldr x4, [x7], #8
68 mov_imm x7, (CCI400_BASE + SLAVE_IFACE_OFFSET( \
70 ldr w8, [x7, #SNOOP_CTRL_REG]
72 mov_imm x7, (CCI400_BASE + SLAVE_IFACE_OFFSET( \
74 ldr w9, [x7, #SNOOP_CTRL_REG]
/device/linaro/bootloader/arm-trusted-firmware/include/plat/arm/common/aarch64/
Darm_macros.S42 mrs x7, id_aa64pfr0_el1
43 ubfx x7, x7, #ID_AA64PFR0_GIC_SHIFT, #ID_AA64PFR0_GIC_WIDTH
44 cmp x7, #1
74 add x7, x16, #GICD_ISPENDR
78 sub x4, x7, x16
86 ldr x4, [x7], #8
Dcci_macros.S26 mov_imm x7, (PLAT_ARM_CCI_BASE + SLAVE_IFACE_OFFSET( \
28 ldr w8, [x7, #SNOOP_CTRL_REG]
30 mov_imm x7, (PLAT_ARM_CCI_BASE + SLAVE_IFACE_OFFSET( \
32 ldr w9, [x7, #SNOOP_CTRL_REG]
/device/linaro/bootloader/edk2/ArmVirtPkg/Library/ArmQemuRelocatablePlatformLib/AARCH64/
DRelocatableVirtHelper.S55 ldr x7, [x9]
56 sub x7, x7, x6
57 add x7, x7, x1
59 str x7, [x9]
69 mov sp, x7
/device/linaro/bootloader/edk2/ArmVirtPkg/Library/ArmXenRelocatablePlatformLib/AARCH64/
DRelocatableVirtHelper.S54 ldr x7, [x9]
55 sub x7, x7, x6
56 add x7, x7, x1
58 str x7, [x9]
68 mov sp, x7
/device/linaro/bootloader/arm-trusted-firmware/plat/nvidia/tegra/include/
Dplat_macros.S43 add x7, x16, #GICD_ISPENDR
47 sub x4, x7, x16
53 ldr x4, [x7], #8
/device/linaro/bootloader/edk2/ArmPkg/Library/ArmLib/AArch64/
DAArch64Support.S300 mov x7, #0x00008000
301 sub x7, x7, #1
302 and x7, x7, x12, lsr #13 // x7 is the max number of the index size (right aligned)
310 lsl x11, x7, x2
317 subs x7, x7, #1 // decrement the index
/device/linaro/bootloader/edk2/ArmPlatformPkg/Library/ArmPlatformStackLib/AArch64/
DArmPlatformStackLib.S31 mov x7, x30
45 mov x30, x7
/device/linaro/bootloader/arm-trusted-firmware/bl31/aarch64/
Dcrash_reporting.S78 mrs x7, tpidr_el3
84 cmp x7, x5
96 ldr x4, [x7], #REG_SIZE
237 str x7, [x0, #REG_SIZE * 7]
/device/linaro/bootloader/arm-trusted-firmware/services/spd/trusty/
Dtrusty_helpers.S45 ldr x7, [x1, #0x28]
51 stp x6, x7, [x8, #32]
/device/linaro/bootloader/edk2/MdeModulePkg/Universal/EbcDxe/AArch64/
DEbcLowLevel.S63 ldr x7, [x9, #56] // Call with 8 arguments
100 ldp x6, x7, [x9, #48]
/device/linaro/bootloader/arm-trusted-firmware/plat/rockchip/rk3399/drivers/pmu/
Dplat_pmu_macros.S54 ldr x7, =(CRU_BASE + 0xc)
56 str w6, [x7, x2]
/device/linaro/bootloader/arm-trusted-firmware/bl32/tsp/aarch64/
Dtsp_exceptions.S26 stp x6, x7, [sp, #0x30]
39 ldp x6, x7, [sp, #0x30]
/device/linaro/bootloader/edk2/ArmPkg/Library/ArmSmcLib/AArch64/
DArmSmc.S21 ldp x6, x7, [x0, #48]
/device/linaro/bootloader/edk2/ArmPkg/Library/ArmHvcLib/AArch64/
DArmHvc.S22 ldp x6, x7, [x0, #48]
/device/linaro/bootloader/OpenPlatformPkg/Platforms/Marvell/Armada/
DArmada70x0.dsc73 gMarvellTokenSpaceGuid.PcdChip1MppSel3|{ 0xA, 0x0, 0x7, 0x0, 0x7, 0x7, 0x7, 0x2, 0x2, 0x0 }
/device/linaro/bootloader/OpenPlatformPkg/Platforms/AMD/Styx/OverdriveBoard/FdtBlob/
Dstyx-overdrive.dts60 interrupts = <0x0 0x7 0x4>,
276 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
338 linux,phandle = <0x7>;
339 phandle = <0x7>;
360 amd,serdes-cdr-rate = <0x2 0x2 0x7>;
378 amd,serdes-cdr-rate = <0x2 0x2 0x7>;
419 clocks = <0x7 0x8>;
/device/linaro/bootloader/OpenPlatformPkg/Platforms/AMD/Styx/Overdrive1000Board/FdtBlob/
Dstyx-overdrive1000.dts60 interrupts = <0x0 0x7 0x4>,
276 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
338 linux,phandle = <0x7>;
339 phandle = <0x7>;
360 amd,serdes-cdr-rate = <0x2 0x2 0x7>;
378 amd,serdes-cdr-rate = <0x2 0x2 0x7>;
419 clocks = <0x7 0x8>;
/device/linaro/bootloader/OpenPlatformPkg/Chips/Hisilicon/Hi1616/D05AcpiTables/
DD05Mcfg.aslc77 0x7, //End Bus Number
91 0x7, //Segment Group Number
/device/linaro/bootloader/arm-trusted-firmware/bl1/aarch64/
Dbl1_exceptions.S200 ldp x6, x7, [x20, #(ENTRY_POINT_INFO_ARGS_OFFSET + 0x30)]
264 bfi x7, x18, #0, #1
/device/linaro/bootloader/edk2/EmbeddedPkg/Scripts/LauterbachT32/
DEfiLoadFv.cmm53 if (&ffsoffset&0x7)!=0
55 &ffsoffset=&ffsoffset+(0x8-(&ffsoffset&0x7))

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