Searched refs:COPY (Results 1 – 25 of 1275) sorted by relevance
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/external/openssh/regress/ |
D | sftp-perm.sh | 22 rm -f ${COPY} ${COPY}.1 23 test -d ${COPY}.dd && { rmdir ${COPY}.dd || fatal "rmdir ${COPY}.dd"; } 86 "put $DATA $COPY" \ 88 "cmp $DATA $COPY" \ 89 "test ! -f $COPY" 93 "chmod 0700 $COPY" \ 94 "touch $COPY; chmod 0400 $COPY" \ 95 "test -x $COPY" \ 96 "test ! -x $COPY" 100 "rm $COPY" \ [all …]
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D | sftp-cmds.sh | 19 QUOTECOPY=${COPY}".\"blah\"" 20 QUOTECOPY_ARG=${COPY}'.\"blah\"' 22 SPACECOPY="${COPY} this has spaces.txt" 23 SPACECOPY_ARG="${COPY}\ this\ has\ spaces.txt" 25 GLOBMETACOPY="${COPY} [metachar].txt" 27 rm -rf ${COPY} ${COPY}.1 ${COPY}.2 ${COPY}.dd ${COPY}.dd2 28 mkdir ${COPY}.dd 68 rm -f ${COPY} 70 echo "get $DATA $COPY" | ${SFTP} -D ${SFTPSERVER} >/dev/null 2>&1 \ 72 cmp $DATA ${COPY} || fail "corrupted copy after get" [all …]
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D | sftp-badcmds.sh | 10 rm -rf ${COPY} ${COPY}.1 ${COPY}.2 ${COPY}.dd 12 rm -f ${COPY} 14 echo "get $NONEXIST $COPY" | ${SFTP} -D ${SFTPSERVER} >/dev/null 2>&1 \ 16 test -f ${COPY} && fail "existing copy after get nonexistent" 18 rm -f ${COPY}.dd/* 23 test -f ${COPY}.dd/$x && fail "existing copy after get nonexistent" 26 rm -f ${COPY} 28 echo "put $NONEXIST $COPY" | ${SFTP} -D ${SFTPSERVER} >/dev/null 2>&1 \ 30 test -f ${COPY} && fail "existing copy after put nonexistent" 32 rm -f ${COPY}.dd/* [all …]
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/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/AArch64/GlobalISel/ |
D | select-binop.mir | 61 # Also check that we constrain the register class of the COPY to GPR32. 76 ; CHECK: [[COPY:%[0-9]+]]:gpr32 = COPY $w0 77 ; CHECK: [[COPY1:%[0-9]+]]:gpr32 = COPY $w1 78 ; CHECK: [[ADDWrr:%[0-9]+]]:gpr32 = ADDWrr [[COPY]], [[COPY1]] 79 ; CHECK: $w0 = COPY [[ADDWrr]] 80 %0(s32) = COPY $w0 81 %1(s32) = COPY $w1 83 $w0 = COPY %2(s32) 102 ; CHECK: [[COPY:%[0-9]+]]:gpr64 = COPY $x0 103 ; CHECK: [[COPY1:%[0-9]+]]:gpr64 = COPY $x1 [all …]
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D | select-fp-casts.mir | 50 ; CHECK: [[COPY:%[0-9]+]]:fpr32 = COPY $s0 51 ; CHECK: [[FCVTHSr:%[0-9]+]]:fpr16 = FCVTHSr [[COPY]] 52 ; CHECK: $h0 = COPY [[FCVTHSr]] 53 %0(s32) = COPY $s0 55 $h0 = COPY %1(s16) 72 ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0 73 ; CHECK: [[FCVTHDr:%[0-9]+]]:fpr16 = FCVTHDr [[COPY]] 74 ; CHECK: $h0 = COPY [[FCVTHDr]] 75 %0(s64) = COPY $d0 77 $h0 = COPY %1(s16) [all …]
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D | regbankselect-default.mir | 85 ; CHECK: [[COPY:%[0-9]+]]:gpr(s32) = COPY $w0 86 ; CHECK: [[ADD:%[0-9]+]]:gpr(s32) = G_ADD [[COPY]], [[COPY]] 87 %0(s32) = COPY $w0 101 ; CHECK: [[COPY:%[0-9]+]]:fpr(<4 x s32>) = COPY $q0 102 ; CHECK: [[ADD:%[0-9]+]]:fpr(<4 x s32>) = G_ADD [[COPY]], [[COPY]] 103 %0(<4 x s32>) = COPY $q0 117 ; CHECK: [[COPY:%[0-9]+]]:gpr(s32) = COPY $w0 118 ; CHECK: [[SUB:%[0-9]+]]:gpr(s32) = G_SUB [[COPY]], [[COPY]] 119 %0(s32) = COPY $w0 133 ; CHECK: [[COPY:%[0-9]+]]:fpr(<4 x s32>) = COPY $q0 [all …]
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D | select-bitcast.mir | 32 ; CHECK: [[COPY:%[0-9]+]]:gpr32all = COPY $w0 33 ; CHECK: $w0 = COPY [[COPY]] 34 %0(s32) = COPY $w0 36 $w0 = COPY %1(s32) 53 ; CHECK: [[COPY:%[0-9]+]]:fpr32 = COPY $s0 54 ; CHECK: $s0 = COPY [[COPY]] 55 %0(s32) = COPY $s0 57 $s0 = COPY %1(s32) 74 ; CHECK: [[COPY:%[0-9]+]]:gpr32all = COPY $w0 75 ; CHECK: [[COPY1:%[0-9]+]]:fpr32 = COPY [[COPY]] [all …]
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D | select-load.mir | 51 ; CHECK: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0 52 ; CHECK: [[LDRXui:%[0-9]+]]:gpr64 = LDRXui [[COPY]], 0 :: (load 8 from %ir.addr) 53 ; CHECK: $x0 = COPY [[LDRXui]] 54 %0(p0) = COPY $x0 56 $x0 = COPY %1(s64) 73 ; CHECK: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0 74 ; CHECK: [[LDRWui:%[0-9]+]]:gpr32 = LDRWui [[COPY]], 0 :: (load 4 from %ir.addr) 75 ; CHECK: $w0 = COPY [[LDRWui]] 76 %0(p0) = COPY $x0 78 $w0 = COPY %1(s32) [all …]
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D | legalize-fptoi.mir | 36 ; CHECK: $w0 = COPY [[FPTOSI]](s32) 39 $w0 = COPY %1 50 ; CHECK: $w0 = COPY [[FPTOUI]](s32) 53 $w0 = COPY %1 64 ; CHECK: $w0 = COPY [[FPTOSI]](s32) 67 $w0 = COPY %1 76 ; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $x0 77 ; CHECK: [[FPTOUI:%[0-9]+]]:_(s32) = G_FPTOUI [[COPY]](s64) 78 ; CHECK: $w0 = COPY [[FPTOUI]](s32) 79 %0:_(s64) = COPY $x0 [all …]
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D | legalize-itofp.mir | 34 ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $w0 35 ; CHECK: [[SITOFP:%[0-9]+]]:_(s32) = G_SITOFP [[COPY]](s32) 36 %0:_(s32) = COPY $w0 38 $w0 = COPY %1 47 ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $w0 48 ; CHECK: [[UITOFP:%[0-9]+]]:_(s32) = G_UITOFP [[COPY]](s32) 49 %0:_(s32) = COPY $w0 51 $w0 = COPY %1 60 ; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $x0 61 ; CHECK: [[SITOFP:%[0-9]+]]:_(s32) = G_SITOFP [[COPY]](s64) [all …]
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D | select-int-ext.mir | 35 ; CHECK: [[COPY:%[0-9]+]]:gpr32all = COPY $w0 36 ; CHECK: [[SUBREG_TO_REG:%[0-9]+]]:gpr64all = SUBREG_TO_REG 0, [[COPY]], %subreg.sub_32 37 ; CHECK: $x0 = COPY [[SUBREG_TO_REG]] 38 %0(s32) = COPY $w0 40 $x0 = COPY %1(s64) 57 ; CHECK: [[COPY:%[0-9]+]]:gpr32 = COPY $w0 58 ; CHECK: [[COPY2:%[0-9]+]]:gpr32all = COPY [[COPY]] 59 ; CHECK: $w0 = COPY [[COPY2]] 60 %2:gpr(s32) = COPY $w0 63 $w0 = COPY %1(s32) [all …]
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D | select-insert-extract.mir | 14 ; CHECK: [[COPY:%[0-9]+]]:gpr32 = COPY $w0 16 ; CHECK: [[SUBREG_TO_REG:%[0-9]+]]:gpr64 = SUBREG_TO_REG 0, [[COPY]], %subreg.sub_32 18 ; CHECK: [[SUBREG_TO_REG1:%[0-9]+]]:gpr64 = SUBREG_TO_REG 0, [[COPY]], %subreg.sub_32 20 ; CHECK: $x0 = COPY [[BFMXri]] 21 ; CHECK: $x1 = COPY [[BFMXri1]] 22 %0:gpr(s32) = COPY $w0 30 $x0 = COPY %2 31 $x1 = COPY %3 43 ; CHECK: [[COPY:%[0-9]+]]:gpr32 = COPY $w0 45 ; CHECK: [[BFMWri:%[0-9]+]]:gpr32 = BFMWri [[DEF]], [[COPY]], 0, 15 [all …]
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D | legalize-ext.mir | 39 ; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $x0 40 ; CHECK: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64) 41 ; CHECK: $w0 = COPY [[TRUNC]](s32) 42 ; CHECK: [[TRUNC1:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64) 43 ; CHECK: $w0 = COPY [[TRUNC1]](s32) 44 ; CHECK: [[TRUNC2:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64) 45 ; CHECK: $w0 = COPY [[TRUNC2]](s32) 46 ; CHECK: [[TRUNC3:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64) 47 ; CHECK: $w0 = COPY [[TRUNC3]](s32) 48 ; CHECK: [[COPY1:%[0-9]+]]:_(s64) = COPY [[COPY]](s64) [all …]
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/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/AMDGPU/GlobalISel/ |
D | legalize-extract-vector-elt.mir | 11 ; CHECK: [[COPY:%[0-9]+]]:_(<2 x s32>) = COPY $vgpr0_vgpr1 13 ; CHECK: [[EVEC:%[0-9]+]]:_(s32) = G_EXTRACT_VECTOR_ELT [[COPY]](<2 x s32>), [[C]](s32) 14 ; CHECK: $vgpr0 = COPY [[EVEC]](s32) 15 %0:_(<2 x s32>) = COPY $vgpr0_vgpr1 18 $vgpr0 = COPY %2 27 ; CHECK: [[COPY:%[0-9]+]]:_(<3 x s32>) = COPY $vgpr0_vgpr1_vgpr2 29 ; CHECK: [[EVEC:%[0-9]+]]:_(s32) = G_EXTRACT_VECTOR_ELT [[COPY]](<3 x s32>), [[C]](s32) 30 ; CHECK: $vgpr0 = COPY [[EVEC]](s32) 31 %0:_(<3 x s32>) = COPY $vgpr0_vgpr1_vgpr2 34 $vgpr0 = COPY %2 [all …]
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D | regbankselect-insert-vector-elt.mir | 12 ; CHECK: [[COPY:%[0-9]+]]:sgpr(<4 x s32>) = COPY $sgpr0_sgpr1_sgpr2_sgpr3 13 ; CHECK: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr5 15 …; CHECK: [[IVEC:%[0-9]+]]:sgpr(<4 x s32>) = G_INSERT_VECTOR_ELT [[COPY]], [[COPY1]](s32), [[C]](s3… 16 ; CHECK: $sgpr0_sgpr1_sgpr2_sgpr3 = COPY [[IVEC]](<4 x s32>) 17 %0:_(<4 x s32>) = COPY $sgpr0_sgpr1_sgpr2_sgpr3 18 %1:_(s32) = COPY $sgpr5 21 $sgpr0_sgpr1_sgpr2_sgpr3 = COPY %3 32 ; CHECK: [[COPY:%[0-9]+]]:vgpr(<4 x s32>) = COPY $vgpr0_vgpr1_vgpr2_vgpr3 33 ; CHECK: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr5 35 ; CHECK: [[COPY2:%[0-9]+]]:vgpr(s32) = COPY [[COPY1]](s32) [all …]
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D | legalize-load.mir | 11 ; CHECK: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1 12 ; CHECK: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p1) :: (load 4, addrspace 1) 13 ; CHECK: $vgpr0 = COPY [[LOAD]](s32) 14 %0:_(p1) = COPY $vgpr0_vgpr1 17 $vgpr0 = COPY %1 27 ; CHECK: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1 28 ; CHECK: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p1) :: (load 4, addrspace 1) 29 ; CHECK: $vgpr0 = COPY [[LOAD]](s32) 30 %0:_(p1) = COPY $vgpr0_vgpr1 33 $vgpr0 = COPY %1 [all …]
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D | legalize-store.mir | 11 ; CHECK: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1 12 ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr2 13 ; CHECK: G_STORE [[COPY1]](s32), [[COPY]](p1) :: (store 4, addrspace 1) 14 %0:_(p1) = COPY $vgpr0_vgpr1 15 %1:_(s32) = COPY $vgpr2 26 ; CHECK: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1 27 ; CHECK: [[COPY1:%[0-9]+]]:_(s64) = COPY $vgpr2_vgpr3 28 ; CHECK: G_STORE [[COPY1]](s64), [[COPY]](p1) :: (store 8, addrspace 1) 29 %0:_(p1) = COPY $vgpr0_vgpr1 30 %1:_(s64) = COPY $vgpr2_vgpr3 [all …]
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/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/X86/GlobalISel/ |
D | select-memop-scalar.mir | 115 ; SSE: [[COPY:%[0-9]+]]:gr64 = COPY $rdi 116 ; SSE: [[MOV8rm:%[0-9]+]]:gr8 = MOV8rm [[COPY]], 1, $noreg, 0, $noreg :: (load 1 from %ir.p1) 117 ; SSE: $al = COPY [[MOV8rm]] 120 ; AVX: [[COPY:%[0-9]+]]:gr64 = COPY $rdi 121 ; AVX: [[MOV8rm:%[0-9]+]]:gr8 = MOV8rm [[COPY]], 1, $noreg, 0, $noreg :: (load 1 from %ir.p1) 122 ; AVX: $al = COPY [[MOV8rm]] 125 ; AVX512F: [[COPY:%[0-9]+]]:gr64 = COPY $rdi 126 … ; AVX512F: [[MOV8rm:%[0-9]+]]:gr8 = MOV8rm [[COPY]], 1, $noreg, 0, $noreg :: (load 1 from %ir.p1) 127 ; AVX512F: $al = COPY [[MOV8rm]] 130 ; AVX512VL: [[COPY:%[0-9]+]]:gr64 = COPY $rdi [all …]
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D | select-fsub-scalar.mir | 43 ; SSE: [[COPY:%[0-9]+]]:vr128 = COPY $xmm0 44 ; SSE: [[COPY1:%[0-9]+]]:fr32 = COPY [[COPY]] 45 ; SSE: [[COPY2:%[0-9]+]]:vr128 = COPY $xmm1 46 ; SSE: [[COPY3:%[0-9]+]]:fr32 = COPY [[COPY2]] 48 ; SSE: [[COPY4:%[0-9]+]]:vr128 = COPY [[SUBSSrr]] 49 ; SSE: $xmm0 = COPY [[COPY4]] 52 ; AVX: [[COPY:%[0-9]+]]:vr128 = COPY $xmm0 53 ; AVX: [[COPY1:%[0-9]+]]:fr32 = COPY [[COPY]] 54 ; AVX: [[COPY2:%[0-9]+]]:vr128 = COPY $xmm1 55 ; AVX: [[COPY3:%[0-9]+]]:fr32 = COPY [[COPY2]] [all …]
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D | select-fadd-scalar.mir | 43 ; SSE: [[COPY:%[0-9]+]]:vr128 = COPY $xmm0 44 ; SSE: [[COPY1:%[0-9]+]]:fr32 = COPY [[COPY]] 45 ; SSE: [[COPY2:%[0-9]+]]:vr128 = COPY $xmm1 46 ; SSE: [[COPY3:%[0-9]+]]:fr32 = COPY [[COPY2]] 48 ; SSE: [[COPY4:%[0-9]+]]:vr128 = COPY [[ADDSSrr]] 49 ; SSE: $xmm0 = COPY [[COPY4]] 52 ; AVX: [[COPY:%[0-9]+]]:vr128 = COPY $xmm0 53 ; AVX: [[COPY1:%[0-9]+]]:fr32 = COPY [[COPY]] 54 ; AVX: [[COPY2:%[0-9]+]]:vr128 = COPY $xmm1 55 ; AVX: [[COPY3:%[0-9]+]]:fr32 = COPY [[COPY2]] [all …]
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D | select-fdiv-scalar.mir | 43 ; SSE: [[COPY:%[0-9]+]]:vr128 = COPY $xmm0 44 ; SSE: [[COPY1:%[0-9]+]]:fr32 = COPY [[COPY]] 45 ; SSE: [[COPY2:%[0-9]+]]:vr128 = COPY $xmm1 46 ; SSE: [[COPY3:%[0-9]+]]:fr32 = COPY [[COPY2]] 48 ; SSE: [[COPY4:%[0-9]+]]:vr128 = COPY [[DIVSSrr]] 49 ; SSE: $xmm0 = COPY [[COPY4]] 52 ; AVX: [[COPY:%[0-9]+]]:vr128 = COPY $xmm0 53 ; AVX: [[COPY1:%[0-9]+]]:fr32 = COPY [[COPY]] 54 ; AVX: [[COPY2:%[0-9]+]]:vr128 = COPY $xmm1 55 ; AVX: [[COPY3:%[0-9]+]]:fr32 = COPY [[COPY2]] [all …]
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D | select-fmul-scalar.mir | 43 ; SSE: [[COPY:%[0-9]+]]:vr128 = COPY $xmm0 44 ; SSE: [[COPY1:%[0-9]+]]:fr32 = COPY [[COPY]] 45 ; SSE: [[COPY2:%[0-9]+]]:vr128 = COPY $xmm1 46 ; SSE: [[COPY3:%[0-9]+]]:fr32 = COPY [[COPY2]] 48 ; SSE: [[COPY4:%[0-9]+]]:vr128 = COPY [[MULSSrr]] 49 ; SSE: $xmm0 = COPY [[COPY4]] 52 ; AVX: [[COPY:%[0-9]+]]:vr128 = COPY $xmm0 53 ; AVX: [[COPY1:%[0-9]+]]:fr32 = COPY [[COPY]] 54 ; AVX: [[COPY2:%[0-9]+]]:vr128 = COPY $xmm1 55 ; AVX: [[COPY3:%[0-9]+]]:fr32 = COPY [[COPY2]] [all …]
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D | legalize-ext.mir | 107 ; X32: [[COPY:%[0-9]+]]:_(s32) = COPY $edi 109 ; X32: [[TRUNC:%[0-9]+]]:_(s8) = G_TRUNC [[COPY]](s32) 111 ; X32: $al = COPY [[AND]](s8) 114 ; X64: [[COPY:%[0-9]+]]:_(s32) = COPY $edi 116 ; X64: [[TRUNC:%[0-9]+]]:_(s8) = G_TRUNC [[COPY]](s32) 118 ; X64: $al = COPY [[AND]](s8) 120 %1:_(s32) = COPY $edi 123 $al = COPY %2(s8) 140 ; X32: [[COPY:%[0-9]+]]:_(s32) = COPY $edi 142 ; X32: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32) [all …]
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D | select-mul-vec.mir | 106 ; CHECK: [[COPY:%[0-9]+]]:vr128 = COPY $xmm0 107 ; CHECK: [[COPY1:%[0-9]+]]:vr128 = COPY $xmm1 108 ; CHECK: [[PMULLWrr:%[0-9]+]]:vr128 = PMULLWrr [[COPY]], [[COPY1]] 109 ; CHECK: $xmm0 = COPY [[PMULLWrr]] 111 %0(<8 x s16>) = COPY $xmm0 112 %1(<8 x s16>) = COPY $xmm1 114 $xmm0 = COPY %2(<8 x s16>) 132 ; CHECK: [[COPY:%[0-9]+]]:vr128 = COPY $xmm0 133 ; CHECK: [[COPY1:%[0-9]+]]:vr128 = COPY $xmm1 134 ; CHECK: [[VPMULLWrr:%[0-9]+]]:vr128 = VPMULLWrr [[COPY]], [[COPY1]] [all …]
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/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/AMDGPU/ |
D | coalescer-subranges-another-prune-error.mir | 26 %0:sreg_64 = COPY $exec 28 undef %2.sub0:sreg_128 = COPY %1 29 %2.sub1:sreg_128 = COPY %1 30 %2.sub2:sreg_128 = COPY %1 31 %2.sub3:sreg_128 = COPY %1 37 %3:sreg_128 = COPY killed %2 38 %4:vreg_128 = COPY killed %3 39 %5:vreg_128 = COPY killed %4 50 %13:sreg_128 = COPY killed %2 52 %15:vreg_128 = COPY killed %13 [all …]
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