1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py 2# RUN: llc -mtriple=aarch64-- -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s 3 4--- | 5 target datalayout = "e-m:o-i64:64-i128:128-n32:64-S128" 6 7 define void @anyext_s64_from_s32() { ret void } 8 define void @anyext_s32_from_s8() { ret void } 9 10 define void @zext_s64_from_s32() { ret void } 11 define void @zext_s32_from_s16() { ret void } 12 define void @zext_s32_from_s8() { ret void } 13 define void @zext_s16_from_s8() { ret void } 14 15 define void @sext_s64_from_s32() { ret void } 16 define void @sext_s32_from_s16() { ret void } 17 define void @sext_s32_from_s8() { ret void } 18 define void @sext_s16_from_s8() { ret void } 19... 20 21--- 22name: anyext_s64_from_s32 23legalized: true 24regBankSelected: true 25 26registers: 27 - { id: 0, class: gpr } 28 - { id: 1, class: gpr } 29 30body: | 31 bb.0: 32 liveins: $w0 33 34 ; CHECK-LABEL: name: anyext_s64_from_s32 35 ; CHECK: [[COPY:%[0-9]+]]:gpr32all = COPY $w0 36 ; CHECK: [[SUBREG_TO_REG:%[0-9]+]]:gpr64all = SUBREG_TO_REG 0, [[COPY]], %subreg.sub_32 37 ; CHECK: $x0 = COPY [[SUBREG_TO_REG]] 38 %0(s32) = COPY $w0 39 %1(s64) = G_ANYEXT %0 40 $x0 = COPY %1(s64) 41... 42 43--- 44name: anyext_s32_from_s8 45legalized: true 46regBankSelected: true 47 48registers: 49 - { id: 0, class: gpr } 50 - { id: 1, class: gpr } 51 52body: | 53 bb.0: 54 liveins: $w0 55 56 ; CHECK-LABEL: name: anyext_s32_from_s8 57 ; CHECK: [[COPY:%[0-9]+]]:gpr32 = COPY $w0 58 ; CHECK: [[COPY2:%[0-9]+]]:gpr32all = COPY [[COPY]] 59 ; CHECK: $w0 = COPY [[COPY2]] 60 %2:gpr(s32) = COPY $w0 61 %0(s8) = G_TRUNC %2 62 %1(s32) = G_ANYEXT %0 63 $w0 = COPY %1(s32) 64... 65 66--- 67name: zext_s64_from_s32 68legalized: true 69regBankSelected: true 70 71registers: 72 - { id: 0, class: gpr } 73 - { id: 1, class: gpr } 74 75body: | 76 bb.0: 77 liveins: $w0 78 79 ; CHECK-LABEL: name: zext_s64_from_s32 80 ; CHECK: [[COPY:%[0-9]+]]:gpr32 = COPY $w0 81 ; CHECK: [[SUBREG_TO_REG:%[0-9]+]]:gpr64 = SUBREG_TO_REG 0, [[COPY]], %subreg.sub_32 82 ; CHECK: [[UBFMXri:%[0-9]+]]:gpr64 = UBFMXri [[SUBREG_TO_REG]], 0, 31 83 ; CHECK: $x0 = COPY [[UBFMXri]] 84 %0(s32) = COPY $w0 85 %1(s64) = G_ZEXT %0 86 $x0 = COPY %1(s64) 87... 88 89--- 90name: zext_s32_from_s16 91legalized: true 92regBankSelected: true 93 94registers: 95 - { id: 0, class: gpr } 96 - { id: 1, class: gpr } 97 98body: | 99 bb.0: 100 liveins: $w0 101 102 ; CHECK-LABEL: name: zext_s32_from_s16 103 ; CHECK: [[COPY:%[0-9]+]]:gpr32 = COPY $w0 104 ; CHECK: [[UBFMWri:%[0-9]+]]:gpr32 = UBFMWri [[COPY]], 0, 15 105 ; CHECK: $w0 = COPY [[UBFMWri]] 106 %2:gpr(s32) = COPY $w0 107 %0(s16) = G_TRUNC %2 108 %1(s32) = G_ZEXT %0 109 $w0 = COPY %1 110... 111 112--- 113name: zext_s32_from_s8 114legalized: true 115regBankSelected: true 116 117registers: 118 - { id: 0, class: gpr } 119 - { id: 1, class: gpr } 120 121body: | 122 bb.0: 123 liveins: $w0 124 125 ; CHECK-LABEL: name: zext_s32_from_s8 126 ; CHECK: [[COPY:%[0-9]+]]:gpr32 = COPY $w0 127 ; CHECK: [[UBFMWri:%[0-9]+]]:gpr32 = UBFMWri [[COPY]], 0, 15 128 ; CHECK: $w0 = COPY [[UBFMWri]] 129 %2:gpr(s32) = COPY $w0 130 %0(s16) = G_TRUNC %2 131 %1(s32) = G_ZEXT %0 132 $w0 = COPY %1(s32) 133... 134 135--- 136name: zext_s16_from_s8 137legalized: true 138regBankSelected: true 139 140registers: 141 - { id: 0, class: gpr } 142 - { id: 1, class: gpr } 143 144body: | 145 bb.0: 146 liveins: $w0 147 148 ; CHECK-LABEL: name: zext_s16_from_s8 149 ; CHECK: [[COPY:%[0-9]+]]:gpr32 = COPY $w0 150 ; CHECK: [[UBFMWri:%[0-9]+]]:gpr32 = UBFMWri [[COPY]], 0, 7 151 ; CHECK: [[COPY2:%[0-9]+]]:gpr32all = COPY [[UBFMWri]] 152 ; CHECK: $w0 = COPY [[COPY2]] 153 %2:gpr(s32) = COPY $w0 154 %0(s8) = G_TRUNC %2 155 %1(s16) = G_ZEXT %0 156 %3:gpr(s32) = G_ANYEXT %1 157 $w0 = COPY %3(s32) 158... 159 160--- 161name: sext_s64_from_s32 162legalized: true 163regBankSelected: true 164 165registers: 166 - { id: 0, class: gpr } 167 - { id: 1, class: gpr } 168 169body: | 170 bb.0: 171 liveins: $w0 172 173 ; CHECK-LABEL: name: sext_s64_from_s32 174 ; CHECK: [[COPY:%[0-9]+]]:gpr32 = COPY $w0 175 ; CHECK: [[SUBREG_TO_REG:%[0-9]+]]:gpr64 = SUBREG_TO_REG 0, [[COPY]], %subreg.sub_32 176 ; CHECK: [[SBFMXri:%[0-9]+]]:gpr64 = SBFMXri [[SUBREG_TO_REG]], 0, 31 177 ; CHECK: $x0 = COPY [[SBFMXri]] 178 %0(s32) = COPY $w0 179 %1(s64) = G_SEXT %0 180 $x0 = COPY %1(s64) 181... 182 183--- 184name: sext_s32_from_s16 185legalized: true 186regBankSelected: true 187 188registers: 189 - { id: 0, class: gpr } 190 - { id: 1, class: gpr } 191 192body: | 193 bb.0: 194 liveins: $w0 195 196 ; CHECK-LABEL: name: sext_s32_from_s16 197 ; CHECK: [[COPY:%[0-9]+]]:gpr32 = COPY $w0 198 ; CHECK: [[SBFMWri:%[0-9]+]]:gpr32 = SBFMWri [[COPY]], 0, 15 199 ; CHECK: $w0 = COPY [[SBFMWri]] 200 %2:gpr(s32) = COPY $w0 201 %0(s16) = G_TRUNC %2 202 %1(s32) = G_SEXT %0 203 $w0 = COPY %1 204... 205 206--- 207name: sext_s32_from_s8 208legalized: true 209regBankSelected: true 210 211registers: 212 - { id: 0, class: gpr } 213 - { id: 1, class: gpr } 214 215body: | 216 bb.0: 217 liveins: $w0 218 219 ; CHECK-LABEL: name: sext_s32_from_s8 220 ; CHECK: [[COPY:%[0-9]+]]:gpr32 = COPY $w0 221 ; CHECK: [[SBFMWri:%[0-9]+]]:gpr32 = SBFMWri [[COPY]], 0, 7 222 ; CHECK: $w0 = COPY [[SBFMWri]] 223 %2:gpr(s32) = COPY $w0 224 %0(s8) = G_TRUNC %2 225 %1(s32) = G_SEXT %0 226 $w0 = COPY %1(s32) 227... 228 229--- 230name: sext_s16_from_s8 231legalized: true 232regBankSelected: true 233 234registers: 235 - { id: 0, class: gpr } 236 - { id: 1, class: gpr } 237 238body: | 239 bb.0: 240 liveins: $w0 241 242 ; CHECK-LABEL: name: sext_s16_from_s8 243 ; CHECK: [[COPY:%[0-9]+]]:gpr32 = COPY $w0 244 ; CHECK: [[SBFMWri:%[0-9]+]]:gpr32 = SBFMWri [[COPY]], 0, 7 245 ; CHECK: [[COPY2:%[0-9]+]]:gpr32all = COPY [[SBFMWri]] 246 ; CHECK: $w0 = COPY [[COPY2]] 247 %2:gpr(s32) = COPY $w0 248 %0(s8) = G_TRUNC %2 249 %1(s16) = G_SEXT %0 250 %3:gpr(s32) = G_ANYEXT %1 251 $w0 = COPY %3(s32) 252... 253