| /external/swiftshader/third_party/llvm-7.0/llvm/lib/CodeGen/ |
| D | RegUsageInfoCollector.cpp | 174 bool CoveredBySubRegs = false; in computeCalleeSavedRegs() local
176 if (RC->CoveredBySubRegs && RC->contains(PReg)) { in computeCalleeSavedRegs()
177 CoveredBySubRegs = true; in computeCalleeSavedRegs()
180 if (!CoveredBySubRegs) in computeCalleeSavedRegs()
|
| D | DetectDeadLanes.cpp | 257 if (RC->CoveredBySubRegs) in transferUsedLanes()
|
| /external/swiftshader/third_party/llvm-7.0/configs/common/lib/Target/X86/ |
| D | X86GenRegisterInfo.inc | 5149 false, /* CoveredBySubRegs */
5161 false, /* CoveredBySubRegs */
5173 false, /* CoveredBySubRegs */
5185 false, /* CoveredBySubRegs */
5197 false, /* CoveredBySubRegs */
5209 false, /* CoveredBySubRegs */
5221 true, /* CoveredBySubRegs */
5233 true, /* CoveredBySubRegs */
5245 false, /* CoveredBySubRegs */
5257 false, /* CoveredBySubRegs */
[all …]
|
| /external/swiftshader/third_party/llvm-7.0/configs/common/lib/Target/Mips/ |
| D | MipsGenRegisterInfo.inc | 4685 false, /* CoveredBySubRegs */
4697 false, /* CoveredBySubRegs */
4709 false, /* CoveredBySubRegs */
4721 false, /* CoveredBySubRegs */
4733 false, /* CoveredBySubRegs */
4745 false, /* CoveredBySubRegs */
4757 false, /* CoveredBySubRegs */
4769 false, /* CoveredBySubRegs */
4781 false, /* CoveredBySubRegs */
4793 false, /* CoveredBySubRegs */
[all …]
|
| /external/swiftshader/third_party/llvm-7.0/llvm/test/TableGen/ |
| D | ConcatenatedSubregs.td | 9 let CoveredBySubRegs = 1;
83 // CHECK: CoveredBySubRegs: 1
87 // CHECK: CoveredBySubRegs: 1
|
| /external/swiftshader/third_party/llvm-7.0/configs/common/lib/Target/ARM/ |
| D | ARMGenRegisterInfo.inc | 5689 false, /* CoveredBySubRegs */
5701 false, /* CoveredBySubRegs */
5713 true, /* CoveredBySubRegs */
5725 true, /* CoveredBySubRegs */
5737 false, /* CoveredBySubRegs */
5749 true, /* CoveredBySubRegs */
5761 true, /* CoveredBySubRegs */
5773 true, /* CoveredBySubRegs */
5785 true, /* CoveredBySubRegs */
5797 true, /* CoveredBySubRegs */
[all …]
|
| /external/swiftshader/third_party/llvm-7.0/configs/common/lib/Target/AArch64/ |
| D | AArch64GenRegisterInfo.inc | 6711 false, /* CoveredBySubRegs */
6723 false, /* CoveredBySubRegs */
6735 false, /* CoveredBySubRegs */
6747 false, /* CoveredBySubRegs */
6759 false, /* CoveredBySubRegs */
6771 false, /* CoveredBySubRegs */
6783 false, /* CoveredBySubRegs */
6795 false, /* CoveredBySubRegs */
6807 false, /* CoveredBySubRegs */
6819 false, /* CoveredBySubRegs */
[all …]
|
| /external/llvm/utils/TableGen/ |
| D | CodeGenRegisters.cpp | 110 CoveredBySubRegs(R->getValueAsBit("CoveredBySubRegs")), in CodeGenRegister()
135 if (CoveredBySubRegs && !ExplicitSubRegs.empty()) in buildObjectGraph()
318 if (!CoveredBySubRegs) in computeSubRegs()
341 if (!SR->CoveredBySubRegs || SR->ExplicitSubRegs.size() <= 1) in computeSubRegs()
977 if (Reg.CoveredBySubRegs) in CodeGenRegBank()
1835 RC.CoveredBySubRegs = true; in computeDerivedInfo()
1838 RC.CoveredBySubRegs &= Reg->CoveredBySubRegs; in computeDerivedInfo()
2118 if (!Super->CoveredBySubRegs || Set.count(Super)) in computeCoveredRegisters()
|
| D | CodeGenRegisters.h | 130 bool CoveredBySubRegs; member
313 bool CoveredBySubRegs; variable
|
| /external/llvm/lib/Target/Hexagon/ |
| D | HexagonRegisterInfo.td | 98 let SubRegIndices = [subreg_loreg, subreg_hireg], CoveredBySubRegs = 1 in {
166 let SubRegIndices = [subreg_loreg, subreg_hireg], CoveredBySubRegs = 1 in {
182 let SubRegIndices = [subreg_loreg, subreg_hireg], CoveredBySubRegs = 1 in {
|
| /external/swiftshader/third_party/llvm-7.0/llvm/utils/TableGen/ |
| D | CodeGenRegisters.cpp | 160 CoveredBySubRegs(R->getValueAsBit("CoveredBySubRegs")), in CodeGenRegister()
186 if (CoveredBySubRegs && !ExplicitSubRegs.empty()) in buildObjectGraph()
368 if (!CoveredBySubRegs) in computeSubRegs()
391 if (!SR->CoveredBySubRegs || SR->ExplicitSubRegs.size() <= 1 || in computeSubRegs()
1152 if (Reg.CoveredBySubRegs) in CodeGenRegBank()
2034 RC.CoveredBySubRegs = true; in computeDerivedInfo()
2037 RC.CoveredBySubRegs &= Reg->CoveredBySubRegs; in computeDerivedInfo()
2324 if (!Super->CoveredBySubRegs || Set.count(Super)) in computeCoveredRegisters()
|
| D | CodeGenRegisters.h | 155 bool CoveredBySubRegs; member
338 bool CoveredBySubRegs; variable
|
| D | RegisterInfoEmitter.cpp | 1374 << (RC.CoveredBySubRegs?"true":"false") in runTargetDesc()
1601 OS << "\tCoveredBySubRegs: " << RC.CoveredBySubRegs << '\n'; in debugDump()
1631 OS << "\tCoveredBySubregs: " << R.CoveredBySubRegs << '\n'; in debugDump()
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Hexagon/ |
| D | HexagonRegisterInfo.td | 97 let SubRegIndices = [isub_lo, isub_hi], CoveredBySubRegs = 1 in {
166 let SubRegIndices = [isub_lo, isub_hi], CoveredBySubRegs = 1 in {
190 let SubRegIndices = [vsub_lo, vsub_hi], CoveredBySubRegs = 1 in {
250 let SubRegIndices = [isub_lo, isub_hi], CoveredBySubRegs = 1 in {
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/SystemZ/ |
| D | SystemZRegisterInfo.td | 68 let CoveredBySubRegs = 1;
76 let CoveredBySubRegs = 1;
199 let CoveredBySubRegs = 1;
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/X86/ |
| D | X86RegisterInfo.td | 113 let SubRegIndices = [sub_8bit, sub_8bit_hi], CoveredBySubRegs = 1 in {
119 let SubRegIndices = [sub_8bit, sub_8bit_hi_phony], CoveredBySubRegs = 1 in {
129 CoveredBySubRegs = 1 in {
141 let SubRegIndices = [sub_16bit, sub_16bit_hi], CoveredBySubRegs = 1 in {
155 CoveredBySubRegs = 1 in {
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Sparc/ |
| D | SparcRegisterInfo.td | 39 let CoveredBySubRegs = 1;
48 let CoveredBySubRegs = 1;
55 let CoveredBySubRegs = 1;
|
| /external/llvm/lib/Target/Sparc/ |
| D | SparcRegisterInfo.td | 39 let CoveredBySubRegs = 1;
48 let CoveredBySubRegs = 1;
55 let CoveredBySubRegs = 1;
|
| /external/llvm/lib/Target/Mips/ |
| D | MipsRegisterInfo.td | 57 let CoveredBySubRegs = 1;
63 let CoveredBySubRegs = 1;
76 let CoveredBySubRegs = 1;
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Mips/ |
| D | MipsRegisterInfo.td | 57 let CoveredBySubRegs = 1;
63 let CoveredBySubRegs = 1;
76 let CoveredBySubRegs = 1;
|
| /external/llvm/include/llvm/Target/ |
| D | TargetRegisterInfo.h | 75 const bool CoveredBySubRegs; variable
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AVR/ |
| D | AVRRegisterInfo.td | 81 CoveredBySubRegs = 1 in
|
| /external/llvm/lib/Target/AVR/ |
| D | AVRRegisterInfo.td | 81 CoveredBySubRegs = 1 in
|
| /external/swiftshader/third_party/llvm-7.0/llvm/include/llvm/CodeGen/ |
| D | TargetRegisterInfo.h | 63 const bool CoveredBySubRegs; variable
|
| /external/llvm/lib/CodeGen/ |
| D | DetectDeadLanes.cpp | 259 if (RC->CoveredBySubRegs) in transferUsedLanes()
|